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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Contains register definitions common to the Book E PowerPC
0004  * specification.  Notice that while the IBM-40x series of CPUs
0005  * are not true Book E PowerPCs, they borrowed a number of features
0006  * before Book E was finalized, and are included here as well.  Unfortunately,
0007  * they sometimes used different locations than true Book E CPUs did.
0008  *
0009  * Copyright 2009-2010 Freescale Semiconductor, Inc.
0010  */
0011 #ifdef __KERNEL__
0012 #ifndef __ASM_POWERPC_REG_BOOKE_H__
0013 #define __ASM_POWERPC_REG_BOOKE_H__
0014 
0015 #include <asm/ppc-opcode.h>
0016 
0017 /* Machine State Register (MSR) Fields */
0018 #define MSR_GS_LG   28  /* Guest state */
0019 #define MSR_UCLE_LG 26  /* User-mode cache lock enable */
0020 #define MSR_SPE_LG  25  /* Enable SPE */
0021 #define MSR_DWE_LG  10  /* Debug Wait Enable */
0022 #define MSR_UBLE_LG 10  /* BTB lock enable (e500) */
0023 #define MSR_IS_LG   MSR_IR_LG /* Instruction Space */
0024 #define MSR_DS_LG   MSR_DR_LG /* Data Space */
0025 #define MSR_PMM_LG  2   /* Performance monitor mark bit */
0026 #define MSR_CM_LG   31  /* Computation Mode (0=32-bit, 1=64-bit) */
0027 
0028 #define MSR_GS      __MASK(MSR_GS_LG)
0029 #define MSR_UCLE    __MASK(MSR_UCLE_LG)
0030 #define MSR_SPE     __MASK(MSR_SPE_LG)
0031 #define MSR_DWE     __MASK(MSR_DWE_LG)
0032 #define MSR_UBLE    __MASK(MSR_UBLE_LG)
0033 #define MSR_IS      __MASK(MSR_IS_LG)
0034 #define MSR_DS      __MASK(MSR_DS_LG)
0035 #define MSR_PMM     __MASK(MSR_PMM_LG)
0036 #define MSR_CM      __MASK(MSR_CM_LG)
0037 
0038 #if defined(CONFIG_PPC_BOOK3E_64)
0039 #define MSR_64BIT   MSR_CM
0040 
0041 #define MSR_        (MSR_ME | MSR_RI | MSR_CE)
0042 #define MSR_KERNEL  (MSR_ | MSR_64BIT)
0043 #define MSR_USER32  (MSR_ | MSR_PR | MSR_EE)
0044 #define MSR_USER64  (MSR_USER32 | MSR_64BIT)
0045 #elif defined (CONFIG_40x)
0046 #define MSR_KERNEL  (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
0047 #define MSR_USER    (MSR_KERNEL|MSR_PR|MSR_EE)
0048 #else
0049 #define MSR_KERNEL  (MSR_ME|MSR_RI|MSR_CE)
0050 #define MSR_USER    (MSR_KERNEL|MSR_PR|MSR_EE)
0051 #endif
0052 
0053 /* Special Purpose Registers (SPRNs)*/
0054 #define SPRN_DECAR  0x036   /* Decrementer Auto Reload Register */
0055 #define SPRN_IVPR   0x03F   /* Interrupt Vector Prefix Register */
0056 #define SPRN_USPRG0 0x100   /* User Special Purpose Register General 0 */
0057 #define SPRN_SPRG3R 0x103   /* Special Purpose Register General 3 Read */
0058 #define SPRN_SPRG4R 0x104   /* Special Purpose Register General 4 Read */
0059 #define SPRN_SPRG5R 0x105   /* Special Purpose Register General 5 Read */
0060 #define SPRN_SPRG6R 0x106   /* Special Purpose Register General 6 Read */
0061 #define SPRN_SPRG7R 0x107   /* Special Purpose Register General 7 Read */
0062 #define SPRN_SPRG4W 0x114   /* Special Purpose Register General 4 Write */
0063 #define SPRN_SPRG5W 0x115   /* Special Purpose Register General 5 Write */
0064 #define SPRN_SPRG6W 0x116   /* Special Purpose Register General 6 Write */
0065 #define SPRN_SPRG7W 0x117   /* Special Purpose Register General 7 Write */
0066 #define SPRN_EPCR   0x133   /* Embedded Processor Control Register */
0067 #define SPRN_DBCR2  0x136   /* Debug Control Register 2 */
0068 #define SPRN_DBCR4  0x233   /* Debug Control Register 4 */
0069 #define SPRN_MSRP   0x137   /* MSR Protect Register */
0070 #define SPRN_IAC3   0x13A   /* Instruction Address Compare 3 */
0071 #define SPRN_IAC4   0x13B   /* Instruction Address Compare 4 */
0072 #define SPRN_DVC1   0x13E   /* Data Value Compare Register 1 */
0073 #define SPRN_DVC2   0x13F   /* Data Value Compare Register 2 */
0074 #define SPRN_LPID   0x152   /* Logical Partition ID */
0075 #define SPRN_MAS8   0x155   /* MMU Assist Register 8 */
0076 #define SPRN_TLB0PS 0x158   /* TLB 0 Page Size Register */
0077 #define SPRN_TLB1PS 0x159   /* TLB 1 Page Size Register */
0078 #define SPRN_MAS5_MAS6  0x15c   /* MMU Assist Register 5 || 6 */
0079 #define SPRN_MAS8_MAS1  0x15d   /* MMU Assist Register 8 || 1 */
0080 #define SPRN_EPTCFG 0x15e   /* Embedded Page Table Config */
0081 #define SPRN_GSPRG0 0x170   /* Guest SPRG0 */
0082 #define SPRN_GSPRG1 0x171   /* Guest SPRG1 */
0083 #define SPRN_GSPRG2 0x172   /* Guest SPRG2 */
0084 #define SPRN_GSPRG3 0x173   /* Guest SPRG3 */
0085 #define SPRN_MAS7_MAS3  0x174   /* MMU Assist Register 7 || 3 */
0086 #define SPRN_MAS0_MAS1  0x175   /* MMU Assist Register 0 || 1 */
0087 #define SPRN_GSRR0  0x17A   /* Guest SRR0 */
0088 #define SPRN_GSRR1  0x17B   /* Guest SRR1 */
0089 #define SPRN_GEPR   0x17C   /* Guest EPR */
0090 #define SPRN_GDEAR  0x17D   /* Guest DEAR */
0091 #define SPRN_GPIR   0x17E   /* Guest PIR */
0092 #define SPRN_GESR   0x17F   /* Guest Exception Syndrome Register */
0093 #define SPRN_IVOR0  0x190   /* Interrupt Vector Offset Register 0 */
0094 #define SPRN_IVOR1  0x191   /* Interrupt Vector Offset Register 1 */
0095 #define SPRN_IVOR2  0x192   /* Interrupt Vector Offset Register 2 */
0096 #define SPRN_IVOR3  0x193   /* Interrupt Vector Offset Register 3 */
0097 #define SPRN_IVOR4  0x194   /* Interrupt Vector Offset Register 4 */
0098 #define SPRN_IVOR5  0x195   /* Interrupt Vector Offset Register 5 */
0099 #define SPRN_IVOR6  0x196   /* Interrupt Vector Offset Register 6 */
0100 #define SPRN_IVOR7  0x197   /* Interrupt Vector Offset Register 7 */
0101 #define SPRN_IVOR8  0x198   /* Interrupt Vector Offset Register 8 */
0102 #define SPRN_IVOR9  0x199   /* Interrupt Vector Offset Register 9 */
0103 #define SPRN_IVOR10 0x19A   /* Interrupt Vector Offset Register 10 */
0104 #define SPRN_IVOR11 0x19B   /* Interrupt Vector Offset Register 11 */
0105 #define SPRN_IVOR12 0x19C   /* Interrupt Vector Offset Register 12 */
0106 #define SPRN_IVOR13 0x19D   /* Interrupt Vector Offset Register 13 */
0107 #define SPRN_IVOR14 0x19E   /* Interrupt Vector Offset Register 14 */
0108 #define SPRN_IVOR15 0x19F   /* Interrupt Vector Offset Register 15 */
0109 #define SPRN_IVOR38 0x1B0   /* Interrupt Vector Offset Register 38 */
0110 #define SPRN_IVOR39 0x1B1   /* Interrupt Vector Offset Register 39 */
0111 #define SPRN_IVOR40 0x1B2   /* Interrupt Vector Offset Register 40 */
0112 #define SPRN_IVOR41 0x1B3   /* Interrupt Vector Offset Register 41 */
0113 #define SPRN_IVOR42 0x1B4   /* Interrupt Vector Offset Register 42 */
0114 #define SPRN_GIVOR2 0x1B8   /* Guest IVOR2 */
0115 #define SPRN_GIVOR3 0x1B9   /* Guest IVOR3 */
0116 #define SPRN_GIVOR4 0x1BA   /* Guest IVOR4 */
0117 #define SPRN_GIVOR8 0x1BB   /* Guest IVOR8 */
0118 #define SPRN_GIVOR13    0x1BC   /* Guest IVOR13 */
0119 #define SPRN_GIVOR14    0x1BD   /* Guest IVOR14 */
0120 #define SPRN_GIVPR  0x1BF   /* Guest IVPR */
0121 #define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
0122 #define SPRN_BBEAR  0x201   /* Branch Buffer Entry Address Register */
0123 #define SPRN_BBTAR  0x202   /* Branch Buffer Target Address Register */
0124 #define SPRN_L1CFG0 0x203   /* L1 Cache Configure Register 0 */
0125 #define SPRN_L1CFG1 0x204   /* L1 Cache Configure Register 1 */
0126 #define SPRN_ATB    0x20E   /* Alternate Time Base */
0127 #define SPRN_ATBL   0x20E   /* Alternate Time Base Lower */
0128 #define SPRN_ATBU   0x20F   /* Alternate Time Base Upper */
0129 #define SPRN_IVOR32 0x210   /* Interrupt Vector Offset Register 32 */
0130 #define SPRN_IVOR33 0x211   /* Interrupt Vector Offset Register 33 */
0131 #define SPRN_IVOR34 0x212   /* Interrupt Vector Offset Register 34 */
0132 #define SPRN_IVOR35 0x213   /* Interrupt Vector Offset Register 35 */
0133 #define SPRN_IVOR36 0x214   /* Interrupt Vector Offset Register 36 */
0134 #define SPRN_IVOR37 0x215   /* Interrupt Vector Offset Register 37 */
0135 #define SPRN_MCARU  0x239   /* Machine Check Address Register Upper */
0136 #define SPRN_MCSRR0 0x23A   /* Machine Check Save and Restore Register 0 */
0137 #define SPRN_MCSRR1 0x23B   /* Machine Check Save and Restore Register 1 */
0138 #define SPRN_MCSR   0x23C   /* Machine Check Status Register */
0139 #define SPRN_MCAR   0x23D   /* Machine Check Address Register */
0140 #define SPRN_DSRR0  0x23E   /* Debug Save and Restore Register 0 */
0141 #define SPRN_DSRR1  0x23F   /* Debug Save and Restore Register 1 */
0142 #define SPRN_SPRG8  0x25C   /* Special Purpose Register General 8 */
0143 #define SPRN_SPRG9  0x25D   /* Special Purpose Register General 9 */
0144 #define SPRN_L1CSR2 0x25E   /* L1 Cache Control and Status Register 2 */
0145 #define SPRN_MAS0   0x270   /* MMU Assist Register 0 */
0146 #define SPRN_MAS1   0x271   /* MMU Assist Register 1 */
0147 #define SPRN_MAS2   0x272   /* MMU Assist Register 2 */
0148 #define SPRN_MAS3   0x273   /* MMU Assist Register 3 */
0149 #define SPRN_MAS4   0x274   /* MMU Assist Register 4 */
0150 #define SPRN_MAS5   0x153   /* MMU Assist Register 5 */
0151 #define SPRN_MAS6   0x276   /* MMU Assist Register 6 */
0152 #define SPRN_PID1   0x279   /* Process ID Register 1 */
0153 #define SPRN_PID2   0x27A   /* Process ID Register 2 */
0154 #define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
0155 #define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
0156 #define SPRN_TLB2CFG    0x2B2   /* TLB 2 Config Register */
0157 #define SPRN_TLB3CFG    0x2B3   /* TLB 3 Config Register */
0158 #define SPRN_EPR    0x2BE   /* External Proxy Register */
0159 #define SPRN_CCR1   0x378   /* Core Configuration Register 1 */
0160 #define SPRN_ZPR    0x3B0   /* Zone Protection Register (40x) */
0161 #define SPRN_MAS7   0x3B0   /* MMU Assist Register 7 */
0162 #define SPRN_MMUCR  0x3B2   /* MMU Control Register */
0163 #define SPRN_CCR0   0x3B3   /* Core Configuration Register 0 */
0164 #define SPRN_EPLC   0x3B3   /* External Process ID Load Context */
0165 #define SPRN_EPSC   0x3B4   /* External Process ID Store Context */
0166 #define SPRN_SGR    0x3B9   /* Storage Guarded Register */
0167 #define SPRN_DCWR   0x3BA   /* Data Cache Write-thru Register */
0168 #define SPRN_SLER   0x3BB   /* Little-endian real mode */
0169 #define SPRN_SU0R   0x3BC   /* "User 0" real mode (40x) */
0170 #define SPRN_DCMP   0x3D1   /* Data TLB Compare Register */
0171 #define SPRN_ICDBDR 0x3D3   /* Instruction Cache Debug Data Register */
0172 #define SPRN_EVPR   0x3D6   /* Exception Vector Prefix Register */
0173 #define SPRN_L1CSR0 0x3F2   /* L1 Cache Control and Status Register 0 */
0174 #define SPRN_L1CSR1 0x3F3   /* L1 Cache Control and Status Register 1 */
0175 #define SPRN_MMUCSR0    0x3F4   /* MMU Control and Status Register 0 */
0176 #define SPRN_MMUCFG 0x3F7   /* MMU Configuration Register */
0177 #define SPRN_BUCSR  0x3F5   /* Branch Unit Control and Status */
0178 #define SPRN_L2CSR0 0x3F9   /* L2 Data Cache Control and Status Register 0 */
0179 #define SPRN_L2CSR1 0x3FA   /* L2 Data Cache Control and Status Register 1 */
0180 #define SPRN_DCCR   0x3FA   /* Data Cache Cacheability Register */
0181 #define SPRN_ICCR   0x3FB   /* Instruction Cache Cacheability Register */
0182 #define SPRN_PWRMGTCR0  0x3FB   /* Power management control register 0 */
0183 #define SPRN_SVR    0x3FF   /* System Version Register */
0184 
0185 /*
0186  * SPRs which have conflicting definitions on true Book E versus classic,
0187  * or IBM 40x.
0188  */
0189 #ifdef CONFIG_BOOKE
0190 #define SPRN_CSRR0  0x03A   /* Critical Save and Restore Register 0 */
0191 #define SPRN_CSRR1  0x03B   /* Critical Save and Restore Register 1 */
0192 #define SPRN_DEAR   0x03D   /* Data Error Address Register */
0193 #define SPRN_ESR    0x03E   /* Exception Syndrome Register */
0194 #define SPRN_PIR    0x11E   /* Processor Identification Register */
0195 #define SPRN_DBSR   0x130   /* Debug Status Register */
0196 #define SPRN_DBCR0  0x134   /* Debug Control Register 0 */
0197 #define SPRN_DBCR1  0x135   /* Debug Control Register 1 */
0198 #define SPRN_IAC1   0x138   /* Instruction Address Compare 1 */
0199 #define SPRN_IAC2   0x139   /* Instruction Address Compare 2 */
0200 #define SPRN_DAC1   0x13C   /* Data Address Compare 1 */
0201 #define SPRN_DAC2   0x13D   /* Data Address Compare 2 */
0202 #define SPRN_TSR    0x150   /* Timer Status Register */
0203 #define SPRN_TCR    0x154   /* Timer Control Register */
0204 #endif /* Book E */
0205 #ifdef CONFIG_40x
0206 #define SPRN_DBCR1  0x3BD   /* Debug Control Register 1 */      
0207 #define SPRN_ESR    0x3D4   /* Exception Syndrome Register */
0208 #define SPRN_DEAR   0x3D5   /* Data Error Address Register */
0209 #define SPRN_TSR    0x3D8   /* Timer Status Register */
0210 #define SPRN_TCR    0x3DA   /* Timer Control Register */
0211 #define SPRN_SRR2   0x3DE   /* Save/Restore Register 2 */
0212 #define SPRN_SRR3   0x3DF   /* Save/Restore Register 3 */
0213 #define SPRN_DBSR   0x3F0   /* Debug Status Register */     
0214 #define SPRN_DBCR0  0x3F2   /* Debug Control Register 0 */
0215 #define SPRN_DAC1   0x3F6   /* Data Address Compare 1 */
0216 #define SPRN_DAC2   0x3F7   /* Data Address Compare 2 */
0217 #define SPRN_CSRR0  SPRN_SRR2 /* Critical Save and Restore Register 0 */
0218 #define SPRN_CSRR1  SPRN_SRR3 /* Critical Save and Restore Register 1 */
0219 #endif
0220 #define SPRN_HACOP  0x15F   /* Hypervisor Available Coprocessor Register */
0221 
0222 /* Bit definitions for CCR1. */
0223 #define CCR1_DPC    0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
0224 #define CCR1_TCS    0x00000080 /* Timer Clock Select */
0225 
0226 /* Bit definitions for PWRMGTCR0. */
0227 #define PWRMGTCR0_PW20_WAIT     (1 << 14) /* PW20 state enable bit */
0228 #define PWRMGTCR0_PW20_ENT_SHIFT    8
0229 #define PWRMGTCR0_PW20_ENT      0x3F00
0230 #define PWRMGTCR0_AV_IDLE_PD_EN     (1 << 22) /* Altivec idle enable */
0231 #define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
0232 #define PWRMGTCR0_AV_IDLE_CNT       0x3F0000
0233 
0234 /* Bit definitions for the MCSR. */
0235 #define MCSR_MCS    0x80000000 /* Machine Check Summary */
0236 #define MCSR_IB     0x40000000 /* Instruction PLB Error */
0237 #define MCSR_DRB    0x20000000 /* Data Read PLB Error */
0238 #define MCSR_DWB    0x10000000 /* Data Write PLB Error */
0239 #define MCSR_TLBP   0x08000000 /* TLB Parity Error */
0240 #define MCSR_ICP    0x04000000 /* I-Cache Parity Error */
0241 #define MCSR_DCSP   0x02000000 /* D-Cache Search Parity Error */
0242 #define MCSR_DCFP   0x01000000 /* D-Cache Flush Parity Error */
0243 #define MCSR_IMPE   0x00800000 /* Imprecise Machine Check Exception */
0244 
0245 #define PPC47x_MCSR_GPR 0x01000000 /* GPR parity error */
0246 #define PPC47x_MCSR_FPR 0x00800000 /* FPR parity error */
0247 #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
0248 
0249 #ifdef CONFIG_E500
0250 /* All e500 */
0251 #define MCSR_MCP    0x80000000UL /* Machine Check Input Pin */
0252 #define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
0253 
0254 /* e500v1/v2 */
0255 #define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
0256 #define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
0257 #define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
0258 #define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
0259 #define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
0260 #define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
0261 #define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
0262 #define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
0263 #define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
0264 #define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
0265 
0266 /* e500mc */
0267 #define MCSR_DCPERR_MC  0x20000000UL /* D-Cache Parity Error */
0268 #define MCSR_L2MMU_MHIT 0x08000000UL /* Hit on multiple TLB entries */
0269 #define MCSR_NMI    0x00100000UL /* Non-Maskable Interrupt */
0270 #define MCSR_MAV    0x00080000UL /* MCAR address valid */
0271 #define MCSR_MEA    0x00040000UL /* MCAR is effective address */
0272 #define MCSR_IF     0x00010000UL /* Instruction Fetch */
0273 #define MCSR_LD     0x00008000UL /* Load */
0274 #define MCSR_ST     0x00004000UL /* Store */
0275 #define MCSR_LDG    0x00002000UL /* Guarded Load */
0276 #define MCSR_TLBSYNC    0x00000002UL /* Multiple tlbsyncs detected */
0277 #define MCSR_BSL2_ERR   0x00000001UL /* Backside L2 cache error */
0278 
0279 #define MSRP_UCLEP  0x04000000 /* Protect MSR[UCLE] */
0280 #define MSRP_DEP    0x00000200 /* Protect MSR[DE] */
0281 #define MSRP_PMMP   0x00000004 /* Protect MSR[PMM] */
0282 #endif
0283 
0284 /* Bit definitions for the HID1 */
0285 #ifdef CONFIG_E500
0286 /* e500v1/v2 */
0287 #define HID1_PLL_CFG_MASK 0xfc000000    /* PLL_CFG input pins */
0288 #define HID1_RFXE   0x00020000  /* Read fault exception enable */
0289 #define HID1_R1DPE  0x00008000  /* R1 data bus parity enable */
0290 #define HID1_R2DPE  0x00004000  /* R2 data bus parity enable */
0291 #define HID1_ASTME  0x00002000  /* Address bus streaming mode enable */
0292 #define HID1_ABE    0x00001000  /* Address broadcast enable */
0293 #define HID1_MPXTT  0x00000400  /* MPX re-map transfer type */
0294 #define HID1_ATS    0x00000080  /* Atomic status */
0295 #define HID1_MID_MASK   0x0000000f  /* MID input pins */
0296 #endif
0297 
0298 /* Bit definitions for the DBSR. */
0299 /*
0300  * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
0301  */
0302 #ifdef CONFIG_BOOKE
0303 #define DBSR_IDE    0x80000000  /* Imprecise Debug Event */
0304 #define DBSR_MRR    0x30000000  /* Most Recent Reset */
0305 #define DBSR_IC     0x08000000  /* Instruction Completion */
0306 #define DBSR_BT     0x04000000  /* Branch Taken */
0307 #define DBSR_IRPT   0x02000000  /* Exception Debug Event */
0308 #define DBSR_TIE    0x01000000  /* Trap Instruction Event */
0309 #define DBSR_IAC1   0x00800000  /* Instr Address Compare 1 Event */
0310 #define DBSR_IAC2   0x00400000  /* Instr Address Compare 2 Event */
0311 #define DBSR_IAC3   0x00200000  /* Instr Address Compare 3 Event */
0312 #define DBSR_IAC4   0x00100000  /* Instr Address Compare 4 Event */
0313 #define DBSR_DAC1R  0x00080000  /* Data Addr Compare 1 Read Event */
0314 #define DBSR_DAC1W  0x00040000  /* Data Addr Compare 1 Write Event */
0315 #define DBSR_DAC2R  0x00020000  /* Data Addr Compare 2 Read Event */
0316 #define DBSR_DAC2W  0x00010000  /* Data Addr Compare 2 Write Event */
0317 #define DBSR_RET    0x00008000  /* Return Debug Event */
0318 #define DBSR_CIRPT  0x00000040  /* Critical Interrupt Taken Event */
0319 #define DBSR_CRET   0x00000020  /* Critical Return Debug Event */
0320 #define DBSR_IAC12ATS   0x00000002  /* Instr Address Compare 1/2 Toggle */
0321 #define DBSR_IAC34ATS   0x00000001  /* Instr Address Compare 3/4 Toggle */
0322 #endif
0323 #ifdef CONFIG_40x
0324 #define DBSR_IC     0x80000000  /* Instruction Completion */
0325 #define DBSR_BT     0x40000000  /* Branch taken */
0326 #define DBSR_IRPT   0x20000000  /* Exception Debug Event */
0327 #define DBSR_TIE    0x10000000  /* Trap Instruction debug Event */
0328 #define DBSR_IAC1   0x04000000  /* Instruction Address Compare 1 Event */
0329 #define DBSR_IAC2   0x02000000  /* Instruction Address Compare 2 Event */
0330 #define DBSR_IAC3   0x00080000  /* Instruction Address Compare 3 Event */
0331 #define DBSR_IAC4   0x00040000  /* Instruction Address Compare 4 Event */
0332 #define DBSR_DAC1R  0x01000000  /* Data Address Compare 1 Read Event */
0333 #define DBSR_DAC1W  0x00800000  /* Data Address Compare 1 Write Event */
0334 #define DBSR_DAC2R  0x00400000  /* Data Address Compare 2 Read Event */
0335 #define DBSR_DAC2W  0x00200000  /* Data Address Compare 2 Write Event */
0336 #endif
0337 
0338 /* Bit definitions related to the ESR. */
0339 #define ESR_MCI     0x80000000  /* Machine Check - Instruction */
0340 #define ESR_IMCP    0x80000000  /* Instr. Machine Check - Protection */
0341 #define ESR_IMCN    0x40000000  /* Instr. Machine Check - Non-config */
0342 #define ESR_IMCB    0x20000000  /* Instr. Machine Check - Bus error */
0343 #define ESR_IMCT    0x10000000  /* Instr. Machine Check - Timeout */
0344 #define ESR_PIL     0x08000000  /* Program Exception - Illegal */
0345 #define ESR_PPR     0x04000000  /* Program Exception - Privileged */
0346 #define ESR_PTR     0x02000000  /* Program Exception - Trap */
0347 #define ESR_FP      0x01000000  /* Floating Point Operation */
0348 #define ESR_DST     0x00800000  /* Storage Exception - Data miss */
0349 #define ESR_DIZ     0x00400000  /* Storage Exception - Zone fault */
0350 #define ESR_ST      0x00800000  /* Store Operation */
0351 #define ESR_DLK     0x00200000  /* Data Cache Locking */
0352 #define ESR_ILK     0x00100000  /* Instr. Cache Locking */
0353 #define ESR_PUO     0x00040000  /* Unimplemented Operation exception */
0354 #define ESR_BO      0x00020000  /* Byte Ordering */
0355 #define ESR_SPV     0x00000080  /* Signal Processing operation */
0356 
0357 /* Bit definitions related to the DBCR0. */
0358 #if defined(CONFIG_40x)
0359 #define DBCR0_EDM   0x80000000  /* External Debug Mode */
0360 #define DBCR0_IDM   0x40000000  /* Internal Debug Mode */
0361 #define DBCR0_RST   0x30000000  /* all the bits in the RST field */
0362 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
0363 #define DBCR0_RST_CHIP  0x20000000  /* Chip Reset */
0364 #define DBCR0_RST_CORE  0x10000000  /* Core Reset */
0365 #define DBCR0_RST_NONE  0x00000000  /* No Reset */
0366 #define DBCR0_IC    0x08000000  /* Instruction Completion */
0367 #define DBCR0_ICMP  DBCR0_IC
0368 #define DBCR0_BT    0x04000000  /* Branch Taken */
0369 #define DBCR0_BRT   DBCR0_BT
0370 #define DBCR0_EDE   0x02000000  /* Exception Debug Event */
0371 #define DBCR0_IRPT  DBCR0_EDE
0372 #define DBCR0_TDE   0x01000000  /* TRAP Debug Event */
0373 #define DBCR0_IA1   0x00800000  /* Instr Addr compare 1 enable */
0374 #define DBCR0_IAC1  DBCR0_IA1
0375 #define DBCR0_IA2   0x00400000  /* Instr Addr compare 2 enable */
0376 #define DBCR0_IAC2  DBCR0_IA2
0377 #define DBCR0_IA12  0x00200000  /* Instr Addr 1-2 range enable */
0378 #define DBCR0_IA12X 0x00100000  /* Instr Addr 1-2 range eXclusive */
0379 #define DBCR0_IA3   0x00080000  /* Instr Addr compare 3 enable */
0380 #define DBCR0_IAC3  DBCR0_IA3
0381 #define DBCR0_IA4   0x00040000  /* Instr Addr compare 4 enable */
0382 #define DBCR0_IAC4  DBCR0_IA4
0383 #define DBCR0_IA34  0x00020000  /* Instr Addr 3-4 range Enable */
0384 #define DBCR0_IA34X 0x00010000  /* Instr Addr 3-4 range eXclusive */
0385 #define DBCR0_IA12T 0x00008000  /* Instr Addr 1-2 range Toggle */
0386 #define DBCR0_IA34T 0x00004000  /* Instr Addr 3-4 range Toggle */
0387 #define DBCR0_FT    0x00000001  /* Freeze Timers on debug event */
0388 
0389 #define dbcr_iac_range(task)    ((task)->thread.debug.dbcr0)
0390 #define DBCR_IAC12I DBCR0_IA12          /* Range Inclusive */
0391 #define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X)  /* Range Exclusive */
0392 #define DBCR_IAC12MODE  (DBCR0_IA12 | DBCR0_IA12X)  /* IAC 1-2 Mode Bits */
0393 #define DBCR_IAC34I DBCR0_IA34          /* Range Inclusive */
0394 #define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X)  /* Range Exclusive */
0395 #define DBCR_IAC34MODE  (DBCR0_IA34 | DBCR0_IA34X)  /* IAC 3-4 Mode Bits */
0396 
0397 /* Bit definitions related to the DBCR1. */
0398 #define DBCR1_DAC1R 0x80000000  /* DAC1 Read Debug Event */
0399 #define DBCR1_DAC2R 0x40000000  /* DAC2 Read Debug Event */
0400 #define DBCR1_DAC1W 0x20000000  /* DAC1 Write Debug Event */
0401 #define DBCR1_DAC2W 0x10000000  /* DAC2 Write Debug Event */
0402 
0403 #define dbcr_dac(task)  ((task)->thread.debug.dbcr1)
0404 #define DBCR_DAC1R  DBCR1_DAC1R
0405 #define DBCR_DAC1W  DBCR1_DAC1W
0406 #define DBCR_DAC2R  DBCR1_DAC2R
0407 #define DBCR_DAC2W  DBCR1_DAC2W
0408 
0409 /*
0410  * Are there any active Debug Events represented in the
0411  * Debug Control Registers?
0412  */
0413 #define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
0414                  DBCR0_IAC3 | DBCR0_IAC4)
0415 #define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \
0416                  DBCR1_DAC1W | DBCR1_DAC2W)
0417 #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
0418                        ((dbcr1) & DBCR1_ACTIVE_EVENTS))
0419 
0420 #elif defined(CONFIG_BOOKE)
0421 #define DBCR0_EDM   0x80000000  /* External Debug Mode */
0422 #define DBCR0_IDM   0x40000000  /* Internal Debug Mode */
0423 #define DBCR0_RST   0x30000000  /* all the bits in the RST field */
0424 /* DBCR0_RST_* is 44x specific and not followed in fsl booke */
0425 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
0426 #define DBCR0_RST_CHIP  0x20000000  /* Chip Reset */
0427 #define DBCR0_RST_CORE  0x10000000  /* Core Reset */
0428 #define DBCR0_RST_NONE  0x00000000  /* No Reset */
0429 #define DBCR0_ICMP  0x08000000  /* Instruction Completion */
0430 #define DBCR0_IC    DBCR0_ICMP
0431 #define DBCR0_BRT   0x04000000  /* Branch Taken */
0432 #define DBCR0_BT    DBCR0_BRT
0433 #define DBCR0_IRPT  0x02000000  /* Exception Debug Event */
0434 #define DBCR0_TDE   0x01000000  /* TRAP Debug Event */
0435 #define DBCR0_TIE   DBCR0_TDE
0436 #define DBCR0_IAC1  0x00800000  /* Instr Addr compare 1 enable */
0437 #define DBCR0_IAC2  0x00400000  /* Instr Addr compare 2 enable */
0438 #define DBCR0_IAC3  0x00200000  /* Instr Addr compare 3 enable */
0439 #define DBCR0_IAC4  0x00100000  /* Instr Addr compare 4 enable */
0440 #define DBCR0_DAC1R 0x00080000  /* DAC 1 Read enable */
0441 #define DBCR0_DAC1W 0x00040000  /* DAC 1 Write enable */
0442 #define DBCR0_DAC2R 0x00020000  /* DAC 2 Read enable */
0443 #define DBCR0_DAC2W 0x00010000  /* DAC 2 Write enable */
0444 #define DBCR0_RET   0x00008000  /* Return Debug Event */
0445 #define DBCR0_CIRPT 0x00000040  /* Critical Interrupt Taken Event */
0446 #define DBCR0_CRET  0x00000020  /* Critical Return Debug Event */
0447 #define DBCR0_FT    0x00000001  /* Freeze Timers on debug event */
0448 
0449 #define dbcr_dac(task)  ((task)->thread.debug.dbcr0)
0450 #define DBCR_DAC1R  DBCR0_DAC1R
0451 #define DBCR_DAC1W  DBCR0_DAC1W
0452 #define DBCR_DAC2R  DBCR0_DAC2R
0453 #define DBCR_DAC2W  DBCR0_DAC2W
0454 
0455 /* Bit definitions related to the DBCR1. */
0456 #define DBCR1_IAC1US    0xC0000000  /* Instr Addr Cmp 1 Sup/User   */
0457 #define DBCR1_IAC1ER    0x30000000  /* Instr Addr Cmp 1 Eff/Real */
0458 #define DBCR1_IAC1ER_01 0x10000000  /* reserved */
0459 #define DBCR1_IAC1ER_10 0x20000000  /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
0460 #define DBCR1_IAC1ER_11 0x30000000  /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
0461 #define DBCR1_IAC2US    0x0C000000  /* Instr Addr Cmp 2 Sup/User   */
0462 #define DBCR1_IAC2ER    0x03000000  /* Instr Addr Cmp 2 Eff/Real */
0463 #define DBCR1_IAC2ER_01 0x01000000  /* reserved */
0464 #define DBCR1_IAC2ER_10 0x02000000  /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
0465 #define DBCR1_IAC2ER_11 0x03000000  /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
0466 #define DBCR1_IAC12M    0x00800000  /* Instr Addr 1-2 range enable */
0467 #define DBCR1_IAC12MX   0x00C00000  /* Instr Addr 1-2 range eXclusive */
0468 #define DBCR1_IAC12AT   0x00010000  /* Instr Addr 1-2 range Toggle */
0469 #define DBCR1_IAC3US    0x0000C000  /* Instr Addr Cmp 3 Sup/User   */
0470 #define DBCR1_IAC3ER    0x00003000  /* Instr Addr Cmp 3 Eff/Real */
0471 #define DBCR1_IAC3ER_01 0x00001000  /* reserved */
0472 #define DBCR1_IAC3ER_10 0x00002000  /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
0473 #define DBCR1_IAC3ER_11 0x00003000  /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
0474 #define DBCR1_IAC4US    0x00000C00  /* Instr Addr Cmp 4 Sup/User   */
0475 #define DBCR1_IAC4ER    0x00000300  /* Instr Addr Cmp 4 Eff/Real */
0476 #define DBCR1_IAC4ER_01 0x00000100  /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
0477 #define DBCR1_IAC4ER_10 0x00000200  /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
0478 #define DBCR1_IAC4ER_11 0x00000300  /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
0479 #define DBCR1_IAC34M    0x00000080  /* Instr Addr 3-4 range enable */
0480 #define DBCR1_IAC34MX   0x000000C0  /* Instr Addr 3-4 range eXclusive */
0481 #define DBCR1_IAC34AT   0x00000001  /* Instr Addr 3-4 range Toggle */
0482 
0483 #define dbcr_iac_range(task)    ((task)->thread.debug.dbcr1)
0484 #define DBCR_IAC12I DBCR1_IAC12M    /* Range Inclusive */
0485 #define DBCR_IAC12X DBCR1_IAC12MX   /* Range Exclusive */
0486 #define DBCR_IAC12MODE  DBCR1_IAC12MX   /* IAC 1-2 Mode Bits */
0487 #define DBCR_IAC34I DBCR1_IAC34M    /* Range Inclusive */
0488 #define DBCR_IAC34X DBCR1_IAC34MX   /* Range Exclusive */
0489 #define DBCR_IAC34MODE  DBCR1_IAC34MX   /* IAC 3-4 Mode Bits */
0490 
0491 /* Bit definitions related to the DBCR2. */
0492 #define DBCR2_DAC1US    0xC0000000  /* Data Addr Cmp 1 Sup/User   */
0493 #define DBCR2_DAC1ER    0x30000000  /* Data Addr Cmp 1 Eff/Real */
0494 #define DBCR2_DAC2US    0x0C000000  /* Data Addr Cmp 2 Sup/User   */
0495 #define DBCR2_DAC2ER    0x03000000  /* Data Addr Cmp 2 Eff/Real */
0496 #define DBCR2_DAC12M    0x00800000  /* DAC 1-2 range enable */
0497 #define DBCR2_DAC12MM   0x00400000  /* DAC 1-2 Mask mode*/
0498 #define DBCR2_DAC12MX   0x00C00000  /* DAC 1-2 range eXclusive */
0499 #define DBCR2_DAC12MODE 0x00C00000  /* DAC 1-2 Mode Bits */
0500 #define DBCR2_DAC12A    0x00200000  /* DAC 1-2 Asynchronous */
0501 #define DBCR2_DVC1M 0x000C0000  /* Data Value Comp 1 Mode */
0502 #define DBCR2_DVC1M_SHIFT   18  /* # of bits to shift DBCR2_DVC1M */
0503 #define DBCR2_DVC2M 0x00030000  /* Data Value Comp 2 Mode */
0504 #define DBCR2_DVC2M_SHIFT   16  /* # of bits to shift DBCR2_DVC2M */
0505 #define DBCR2_DVC1BE    0x00000F00  /* Data Value Comp 1 Byte */
0506 #define DBCR2_DVC1BE_SHIFT  8   /* # of bits to shift DBCR2_DVC1BE */
0507 #define DBCR2_DVC2BE    0x0000000F  /* Data Value Comp 2 Byte */
0508 #define DBCR2_DVC2BE_SHIFT  0   /* # of bits to shift DBCR2_DVC2BE */
0509 
0510 /*
0511  * Are there any active Debug Events represented in the
0512  * Debug Control Registers?
0513  */
0514 #define DBCR0_ACTIVE_EVENTS  (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
0515                   DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
0516                   DBCR0_DAC1W  | DBCR0_DAC2R | DBCR0_DAC2W)
0517 #define DBCR1_ACTIVE_EVENTS 0
0518 
0519 #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
0520                        ((dbcr1) & DBCR1_ACTIVE_EVENTS))
0521 #endif /* #elif defined(CONFIG_BOOKE) */
0522 
0523 /* Bit definitions related to the TCR. */
0524 #define TCR_WP(x)   (((x)&0x3)<<30) /* WDT Period */
0525 #define TCR_WP_MASK TCR_WP(3)
0526 #define WP_2_17     0       /* 2^17 clocks */
0527 #define WP_2_21     1       /* 2^21 clocks */
0528 #define WP_2_25     2       /* 2^25 clocks */
0529 #define WP_2_29     3       /* 2^29 clocks */
0530 #define TCR_WRC(x)  (((x)&0x3)<<28) /* WDT Reset Control */
0531 #define TCR_WRC_MASK    TCR_WRC(3)
0532 #define WRC_NONE    0       /* No reset will occur */
0533 #define WRC_CORE    1       /* Core reset will occur */
0534 #define WRC_CHIP    2       /* Chip reset will occur */
0535 #define WRC_SYSTEM  3       /* System reset will occur */
0536 #define TCR_WIE     0x08000000  /* WDT Interrupt Enable */
0537 #define TCR_PIE     0x04000000  /* PIT Interrupt Enable */
0538 #define TCR_DIE     TCR_PIE     /* DEC Interrupt Enable */
0539 #define TCR_FP(x)   (((x)&0x3)<<24) /* FIT Period */
0540 #define TCR_FP_MASK TCR_FP(3)
0541 #define FP_2_9      0       /* 2^9 clocks */
0542 #define FP_2_13     1       /* 2^13 clocks */
0543 #define FP_2_17     2       /* 2^17 clocks */
0544 #define FP_2_21     3       /* 2^21 clocks */
0545 #define TCR_FIE     0x00800000  /* FIT Interrupt Enable */
0546 #define TCR_ARE     0x00400000  /* Auto Reload Enable */
0547 
0548 #ifdef CONFIG_E500
0549 #define TCR_GET_WP(tcr)  ((((tcr) & 0xC0000000) >> 30) | \
0550                   (((tcr) & 0x1E0000) >> 15))
0551 #else
0552 #define TCR_GET_WP(tcr)  (((tcr) & 0xC0000000) >> 30)
0553 #endif
0554 
0555 /* Bit definitions for the TSR. */
0556 #define TSR_ENW     0x80000000  /* Enable Next Watchdog */
0557 #define TSR_WIS     0x40000000  /* WDT Interrupt Status */
0558 #define TSR_WRS(x)  (((x)&0x3)<<28) /* WDT Reset Status */
0559 #define WRS_NONE    0       /* No WDT reset occurred */
0560 #define WRS_CORE    1       /* WDT forced core reset */
0561 #define WRS_CHIP    2       /* WDT forced chip reset */
0562 #define WRS_SYSTEM  3       /* WDT forced system reset */
0563 #define TSR_PIS     0x08000000  /* PIT Interrupt Status */
0564 #define TSR_DIS     TSR_PIS     /* DEC Interrupt Status */
0565 #define TSR_FIS     0x04000000  /* FIT Interrupt Status */
0566 
0567 /* Bit definitions for the DCCR. */
0568 #define DCCR_NOCACHE    0       /* Noncacheable */
0569 #define DCCR_CACHE  1       /* Cacheable */
0570 
0571 /* Bit definitions for DCWR. */
0572 #define DCWR_COPY   0       /* Copy-back */
0573 #define DCWR_WRITE  1       /* Write-through */
0574 
0575 /* Bit definitions for ICCR. */
0576 #define ICCR_NOCACHE    0       /* Noncacheable */
0577 #define ICCR_CACHE  1       /* Cacheable */
0578 
0579 /* Bit definitions for L1CSR0. */
0580 #define L1CSR0_CPE  0x00010000  /* Data Cache Parity Enable */
0581 #define L1CSR0_CUL  0x00000400  /* Data Cache Unable to Lock */
0582 #define L1CSR0_CLFC 0x00000100  /* Cache Lock Bits Flash Clear */
0583 #define L1CSR0_DCFI 0x00000002  /* Data Cache Flash Invalidate */
0584 #define L1CSR0_CFI  0x00000002  /* Cache Flash Invalidate */
0585 #define L1CSR0_DCE  0x00000001  /* Data Cache Enable */
0586 
0587 /* Bit definitions for L1CSR1. */
0588 #define L1CSR1_CPE  0x00010000  /* Instruction Cache Parity Enable */
0589 #define L1CSR1_ICLFR    0x00000100  /* Instr Cache Lock Bits Flash Reset */
0590 #define L1CSR1_ICFI 0x00000002  /* Instr Cache Flash Invalidate */
0591 #define L1CSR1_ICE  0x00000001  /* Instr Cache Enable */
0592 
0593 /* Bit definitions for L1CSR2. */
0594 #define L1CSR2_DCWS 0x40000000  /* Data Cache write shadow */
0595 
0596 /* Bit definitions for BUCSR. */
0597 #define BUCSR_STAC_EN   0x01000000  /* Segment Target Address Cache */
0598 #define BUCSR_LS_EN 0x00400000  /* Link Stack */
0599 #define BUCSR_BBFI  0x00000200  /* Branch Buffer flash invalidate */
0600 #define BUCSR_BPEN  0x00000001  /* Branch prediction enable */
0601 #define BUCSR_INIT  (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
0602 
0603 /* Bit definitions for L2CSR0. */
0604 #define L2CSR0_L2E  0x80000000  /* L2 Cache Enable */
0605 #define L2CSR0_L2PE 0x40000000  /* L2 Cache Parity/ECC Enable */
0606 #define L2CSR0_L2WP 0x1c000000  /* L2 I/D Way Partioning */
0607 #define L2CSR0_L2CM 0x03000000  /* L2 Cache Coherency Mode */
0608 #define L2CSR0_L2FI 0x00200000  /* L2 Cache Flash Invalidate */
0609 #define L2CSR0_L2IO 0x00100000  /* L2 Cache Instruction Only */
0610 #define L2CSR0_L2DO 0x00010000  /* L2 Cache Data Only */
0611 #define L2CSR0_L2REP    0x00003000  /* L2 Line Replacement Algo */
0612 #define L2CSR0_L2FL 0x00000800  /* L2 Cache Flush */
0613 #define L2CSR0_L2LFC    0x00000400  /* L2 Cache Lock Flash Clear */
0614 #define L2CSR0_L2LOA    0x00000080  /* L2 Cache Lock Overflow Allocate */
0615 #define L2CSR0_L2LO 0x00000020  /* L2 Cache Lock Overflow */
0616 
0617 /* Bit definitions for SGR. */
0618 #define SGR_NORMAL  0       /* Speculative fetching allowed. */
0619 #define SGR_GUARDED 1       /* Speculative fetching disallowed. */
0620 
0621 /* Bit definitions for EPCR */
0622 #define SPRN_EPCR_EXTGS     0x80000000  /* External Input interrupt
0623                          * directed to Guest state */
0624 #define SPRN_EPCR_DTLBGS    0x40000000  /* Data TLB Error interrupt
0625                          * directed to guest state */
0626 #define SPRN_EPCR_ITLBGS    0x20000000  /* Instr. TLB error interrupt
0627                          * directed to guest state */
0628 #define SPRN_EPCR_DSIGS     0x10000000  /* Data Storage interrupt
0629                          * directed to guest state */
0630 #define SPRN_EPCR_ISIGS     0x08000000  /* Instr. Storage interrupt
0631                          * directed to guest state */
0632 #define SPRN_EPCR_DUVD      0x04000000  /* Disable Hypervisor Debug */
0633 #define SPRN_EPCR_ICM       0x02000000  /* Interrupt computation mode
0634                          * (copied to MSR:CM on intr) */
0635 #define SPRN_EPCR_GICM      0x01000000  /* Guest Interrupt Comp. mode */
0636 #define SPRN_EPCR_DGTMI     0x00800000  /* Disable TLB Guest Management
0637                          * instructions */
0638 #define SPRN_EPCR_DMIUH     0x00400000  /* Disable MAS Interrupt updates
0639                          * for hypervisor */
0640 
0641 /* Bit definitions for EPLC/EPSC */
0642 #define EPC_EPR     0x80000000 /* 1 = user, 0 = kernel */
0643 #define EPC_EPR_SHIFT   31
0644 #define EPC_EAS     0x40000000 /* Address Space */
0645 #define EPC_EAS_SHIFT   30
0646 #define EPC_EGS     0x20000000 /* 1 = guest, 0 = hypervisor */
0647 #define EPC_EGS_SHIFT   29
0648 #define EPC_ELPID   0x00ff0000
0649 #define EPC_ELPID_SHIFT 16
0650 #define EPC_EPID    0x00003fff
0651 #define EPC_EPID_SHIFT  0
0652 
0653 /* Some 476 specific registers */
0654 #define SPRN_SSPCR      830
0655 #define SPRN_USPCR      831
0656 #define SPRN_ISPCR      829
0657 #define SPRN_MMUBE0     820
0658 #define MMUBE0_IBE0_SHIFT   24
0659 #define MMUBE0_IBE1_SHIFT   16
0660 #define MMUBE0_IBE2_SHIFT   8
0661 #define MMUBE0_VBE0     0x00000004
0662 #define MMUBE0_VBE1     0x00000002
0663 #define MMUBE0_VBE2     0x00000001
0664 #define SPRN_MMUBE1     821
0665 #define MMUBE1_IBE3_SHIFT   24
0666 #define MMUBE1_IBE4_SHIFT   16
0667 #define MMUBE1_IBE5_SHIFT   8
0668 #define MMUBE1_VBE3     0x00000004
0669 #define MMUBE1_VBE4     0x00000002
0670 #define MMUBE1_VBE5     0x00000001
0671 
0672 #define TMRN_TMCFG0      16 /* Thread Management Configuration Register 0 */
0673 #define TMRN_TMCFG0_NPRIBITS       0x003f0000 /* Bits of thread priority */
0674 #define TMRN_TMCFG0_NPRIBITS_SHIFT 16
0675 #define TMRN_TMCFG0_NATHRD         0x00003f00 /* Number of active threads */
0676 #define TMRN_TMCFG0_NATHRD_SHIFT   8
0677 #define TMRN_TMCFG0_NTHRD          0x0000003f /* Number of threads */
0678 #define TMRN_IMSR0  0x120   /* Initial MSR Register 0 (e6500) */
0679 #define TMRN_IMSR1  0x121   /* Initial MSR Register 1 (e6500) */
0680 #define TMRN_INIA0  0x140   /* Next Instruction Address Register 0 */
0681 #define TMRN_INIA1  0x141   /* Next Instruction Address Register 1 */
0682 #define SPRN_TENSR  0x1b5   /* Thread Enable Status Register */
0683 #define SPRN_TENS   0x1b6   /* Thread Enable Set Register */
0684 #define SPRN_TENC   0x1b7   /* Thread Enable Clear Register */
0685 
0686 #define TEN_THREAD(x)   (1 << (x))
0687 
0688 #ifndef __ASSEMBLY__
0689 #define mftmr(rn)   ({unsigned long rval; \
0690             asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
0691 #define mttmr(rn, v)    asm volatile(MTTMR(rn, %0) : \
0692                      : "r" ((unsigned long)(v)) \
0693                      : "memory")
0694 
0695 extern unsigned long global_dbcr0[];
0696 
0697 #endif /* !__ASSEMBLY__ */
0698 
0699 #endif /* __ASM_POWERPC_REG_BOOKE_H__ */
0700 #endif /* __KERNEL__ */
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