include/asm/reg_8xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Contains register definitions common to PowerPC 8xx CPUs.  Notice
0004  */
0005 #ifndef _ASM_POWERPC_REG_8xx_H
0006 #define _ASM_POWERPC_REG_8xx_H
0007
0008 /* Cache control on the MPC8xx is provided through some additional
0009  * special purpose registers.
0010  */
0011 #define SPRN_IC_CST 560 /* Instruction cache control/status */
0012 #define SPRN_IC_ADR 561 /* Address needed for some commands */
0013 #define SPRN_IC_DAT 562 /* Read-only data register */
0014 #define SPRN_DC_CST 568 /* Data cache control/status */
0015 #define SPRN_DC_ADR 569 /* Address needed for some commands */
0016 #define SPRN_DC_DAT 570 /* Read-only data register */
0017
0018 /* Misc Debug */
0019 #define SPRN_DPDR   630
0020 #define SPRN_MI_CAM 816
0021 #define SPRN_MI_RAM0    817
0022 #define SPRN_MI_RAM1    818
0023 #define SPRN_MD_CAM 824
0024 #define SPRN_MD_RAM0    825
0025 #define SPRN_MD_RAM1    826
0026
0027 /* Special MSR manipulation registers */
0028 #define SPRN_EIE    80  /* External interrupt enable (EE=1, RI=1) */
0029 #define SPRN_EID    81  /* External interrupt disable (EE=0, RI=1) */
0030 #define SPRN_NRI    82  /* Non recoverable interrupt (EE=0, RI=0) */
0031
0032 /* Debug registers */
0033 #define SPRN_CMPA   144
0034 #define SPRN_COUNTA 150
0035 #define SPRN_CMPE   152
0036 #define SPRN_CMPF   153
0037 #define SPRN_LCTRL1 156
0038 #define   LCTRL1_CTE_GT     0xc0000000
0039 #define   LCTRL1_CTF_LT     0x14000000
0040 #define   LCTRL1_CRWE_RW    0x00000000
0041 #define   LCTRL1_CRWE_RO    0x00040000
0042 #define   LCTRL1_CRWE_WO    0x000c0000
0043 #define   LCTRL1_CRWF_RW    0x00000000
0044 #define   LCTRL1_CRWF_RO    0x00010000
0045 #define   LCTRL1_CRWF_WO    0x00030000
0046 #define SPRN_LCTRL2 157
0047 #define   LCTRL2_LW0EN      0x80000000
0048 #define   LCTRL2_LW0LA_E    0x00000000
0049 #define   LCTRL2_LW0LA_F    0x04000000
0050 #define   LCTRL2_LW0LA_EandF    0x08000000
0051 #define   LCTRL2_LW0LADC    0x02000000
0052 #define   LCTRL2_SLW0EN     0x00000002
0053 #ifdef CONFIG_PPC_8xx
0054 #define SPRN_ICTRL  158
0055 #endif
0056 #define SPRN_BAR    159
0057
0058 /* Commands.  Only the first few are available to the instruction cache.
0059 */
0060 #define IDC_ENABLE  0x02000000  /* Cache enable */
0061 #define IDC_DISABLE 0x04000000  /* Cache disable */
0062 #define IDC_LDLCK   0x06000000  /* Load and lock */
0063 #define IDC_UNLINE  0x08000000  /* Unlock line */
0064 #define IDC_UNALL   0x0a000000  /* Unlock all */
0065 #define IDC_INVALL  0x0c000000  /* Invalidate all */
0066
0067 #define DC_FLINE    0x0e000000  /* Flush data cache line */
0068 #define DC_SFWT     0x01000000  /* Set forced writethrough mode */
0069 #define DC_CFWT     0x03000000  /* Clear forced writethrough mode */
0070 #define DC_SLES     0x05000000  /* Set little endian swap mode */
0071 #define DC_CLES     0x07000000  /* Clear little endian swap mode */
0072
0073 /* Status.
0074 */
0075 #define IDC_ENABLED 0x80000000  /* Cache is enabled */
0076 #define IDC_CERR1   0x00200000  /* Cache error 1 */
0077 #define IDC_CERR2   0x00100000  /* Cache error 2 */
0078 #define IDC_CERR3   0x00080000  /* Cache error 3 */
0079
0080 #define DC_DFWT     0x40000000  /* Data cache is forced write through */
0081 #define DC_LES      0x20000000  /* Caches are little endian mode */
0082
0083 #endif /* _ASM_POWERPC_REG_8xx_H */