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0008 #ifndef _ASM_POWERPC_PS3GPU_H
0009 #define _ASM_POWERPC_PS3GPU_H
0010
0011 #include <linux/mutex.h>
0012
0013 #include <asm/lv1call.h>
0014
0015
0016 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC 0x101
0017 #define L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP 0x102
0018
0019 #define L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP 0x600
0020 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
0021 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT_SYNC 0x602
0022 #define L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE 0x603
0023
0024 #define L1GPU_FB_BLIT_WAIT_FOR_COMPLETION (1ULL << 32)
0025
0026 #define L1GPU_DISPLAY_SYNC_HSYNC 1
0027 #define L1GPU_DISPLAY_SYNC_VSYNC 2
0028
0029
0030
0031 extern struct mutex ps3_gpu_mutex;
0032
0033
0034 static inline int lv1_gpu_display_sync(u64 context_handle, u64 head,
0035 u64 ddr_offset)
0036 {
0037 return lv1_gpu_context_attribute(context_handle,
0038 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_SYNC,
0039 head, ddr_offset, 0, 0);
0040 }
0041
0042 static inline int lv1_gpu_display_flip(u64 context_handle, u64 head,
0043 u64 ddr_offset)
0044 {
0045 return lv1_gpu_context_attribute(context_handle,
0046 L1GPU_CONTEXT_ATTRIBUTE_DISPLAY_FLIP,
0047 head, ddr_offset, 0, 0);
0048 }
0049
0050 static inline int lv1_gpu_fb_setup(u64 context_handle, u64 xdr_lpar,
0051 u64 xdr_size, u64 ioif_offset)
0052 {
0053 return lv1_gpu_context_attribute(context_handle,
0054 L1GPU_CONTEXT_ATTRIBUTE_FB_SETUP,
0055 xdr_lpar, xdr_size, ioif_offset, 0);
0056 }
0057
0058 static inline int lv1_gpu_fb_blit(u64 context_handle, u64 ddr_offset,
0059 u64 ioif_offset, u64 sync_width, u64 pitch)
0060 {
0061 return lv1_gpu_context_attribute(context_handle,
0062 L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
0063 ddr_offset, ioif_offset, sync_width,
0064 pitch);
0065 }
0066
0067 static inline int lv1_gpu_fb_close(u64 context_handle)
0068 {
0069 return lv1_gpu_context_attribute(context_handle,
0070 L1GPU_CONTEXT_ATTRIBUTE_FB_CLOSE, 0,
0071 0, 0, 0);
0072 }
0073
0074 #endif