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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef _ASM_POWERPC_PROCESSOR_H
0003 #define _ASM_POWERPC_PROCESSOR_H
0004 
0005 /*
0006  * Copyright (C) 2001 PPC 64 Team, IBM Corp
0007  */
0008 
0009 #include <vdso/processor.h>
0010 
0011 #include <asm/reg.h>
0012 
0013 #ifdef CONFIG_VSX
0014 #define TS_FPRWIDTH 2
0015 
0016 #ifdef __BIG_ENDIAN__
0017 #define TS_FPROFFSET 0
0018 #define TS_VSRLOWOFFSET 1
0019 #else
0020 #define TS_FPROFFSET 1
0021 #define TS_VSRLOWOFFSET 0
0022 #endif
0023 
0024 #else
0025 #define TS_FPRWIDTH 1
0026 #define TS_FPROFFSET 0
0027 #endif
0028 
0029 #ifdef CONFIG_PPC64
0030 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
0031 #define PPR_PRIORITY 3
0032 #ifdef __ASSEMBLY__
0033 #define DEFAULT_PPR (PPR_PRIORITY << 50)
0034 #else
0035 #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
0036 #endif /* __ASSEMBLY__ */
0037 #endif /* CONFIG_PPC64 */
0038 
0039 #ifndef __ASSEMBLY__
0040 #include <linux/types.h>
0041 #include <linux/thread_info.h>
0042 #include <asm/ptrace.h>
0043 #include <asm/hw_breakpoint.h>
0044 
0045 /* We do _not_ want to define new machine types at all, those must die
0046  * in favor of using the device-tree
0047  * -- BenH.
0048  */
0049 
0050 /* PREP sub-platform types. Unused */
0051 #define _PREP_Motorola  0x01    /* motorola prep */
0052 #define _PREP_Firm  0x02    /* firmworks prep */
0053 #define _PREP_IBM   0x00    /* ibm prep */
0054 #define _PREP_Bull  0x03    /* bull prep */
0055 
0056 /* CHRP sub-platform types. These are arbitrary */
0057 #define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
0058 #define _CHRP_IBM   0x05    /* IBM chrp, the longtrail and longtrail 2 */
0059 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
0060 #define _CHRP_briq  0x07    /* TotalImpact's briQ */
0061 
0062 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
0063 
0064 extern int _chrp_type;
0065 
0066 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
0067 
0068 #ifdef __KERNEL__
0069 
0070 #ifdef CONFIG_PPC64
0071 #include <asm/task_size_64.h>
0072 #else
0073 #include <asm/task_size_32.h>
0074 #endif
0075 
0076 struct task_struct;
0077 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
0078 void release_thread(struct task_struct *);
0079 
0080 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
0081 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
0082 
0083 /* FP and VSX 0-31 register set */
0084 struct thread_fp_state {
0085     u64 fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
0086     u64 fpscr;      /* Floating point status */
0087 };
0088 
0089 /* Complete AltiVec register set including VSCR */
0090 struct thread_vr_state {
0091     vector128   vr[32] __attribute__((aligned(16)));
0092     vector128   vscr __attribute__((aligned(16)));
0093 };
0094 
0095 struct debug_reg {
0096 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
0097     /*
0098      * The following help to manage the use of Debug Control Registers
0099      * om the BookE platforms.
0100      */
0101     uint32_t    dbcr0;
0102     uint32_t    dbcr1;
0103 #ifdef CONFIG_BOOKE
0104     uint32_t    dbcr2;
0105 #endif
0106     /*
0107      * The stored value of the DBSR register will be the value at the
0108      * last debug interrupt. This register can only be read from the
0109      * user (will never be written to) and has value while helping to
0110      * describe the reason for the last debug trap.  Torez
0111      */
0112     uint32_t    dbsr;
0113     /*
0114      * The following will contain addresses used by debug applications
0115      * to help trace and trap on particular address locations.
0116      * The bits in the Debug Control Registers above help define which
0117      * of the following registers will contain valid data and/or addresses.
0118      */
0119     unsigned long   iac1;
0120     unsigned long   iac2;
0121 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
0122     unsigned long   iac3;
0123     unsigned long   iac4;
0124 #endif
0125     unsigned long   dac1;
0126     unsigned long   dac2;
0127 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
0128     unsigned long   dvc1;
0129     unsigned long   dvc2;
0130 #endif
0131 #endif
0132 };
0133 
0134 struct thread_struct {
0135     unsigned long   ksp;        /* Kernel stack pointer */
0136 
0137 #ifdef CONFIG_PPC64
0138     unsigned long   ksp_vsid;
0139 #endif
0140     struct pt_regs  *regs;      /* Pointer to saved register state */
0141 #ifdef CONFIG_BOOKE
0142     /* BookE base exception scratch space; align on cacheline */
0143     unsigned long   normsave[8] ____cacheline_aligned;
0144 #endif
0145 #ifdef CONFIG_PPC32
0146     void        *pgdir;     /* root of page-table tree */
0147 #ifdef CONFIG_PPC_RTAS
0148     unsigned long   rtas_sp;    /* stack pointer for when in RTAS */
0149 #endif
0150 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
0151     unsigned long   kuap;       /* opened segments for user access */
0152 #endif
0153     unsigned long   srr0;
0154     unsigned long   srr1;
0155     unsigned long   dar;
0156     unsigned long   dsisr;
0157 #ifdef CONFIG_PPC_BOOK3S_32
0158     unsigned long   r0, r3, r4, r5, r6, r8, r9, r11;
0159     unsigned long   lr, ctr;
0160     unsigned long   sr0;
0161 #endif
0162 #endif /* CONFIG_PPC32 */
0163 #if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP)
0164     unsigned long   pid;    /* value written in PID reg. at interrupt exit */
0165 #endif
0166     /* Debug Registers */
0167     struct debug_reg debug;
0168 #ifdef CONFIG_PPC_FPU_REGS
0169     struct thread_fp_state  fp_state;
0170     struct thread_fp_state  *fp_save_area;
0171 #endif
0172     int     fpexc_mode; /* floating-point exception mode */
0173     unsigned int    align_ctl;  /* alignment handling control */
0174 #ifdef CONFIG_HAVE_HW_BREAKPOINT
0175     struct perf_event *ptrace_bps[HBP_NUM_MAX];
0176     /*
0177      * Helps identify source of single-step exception and subsequent
0178      * hw-breakpoint enablement
0179      */
0180     struct perf_event *last_hit_ubp[HBP_NUM_MAX];
0181 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
0182     struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
0183     unsigned long   trap_nr;    /* last trap # on this thread */
0184     u8 load_slb;            /* Ages out SLB preload cache entries */
0185     u8 load_fp;
0186 #ifdef CONFIG_ALTIVEC
0187     u8 load_vec;
0188     struct thread_vr_state vr_state;
0189     struct thread_vr_state *vr_save_area;
0190     unsigned long   vrsave;
0191     int     used_vr;    /* set if process has used altivec */
0192 #endif /* CONFIG_ALTIVEC */
0193 #ifdef CONFIG_VSX
0194     /* VSR status */
0195     int     used_vsr;   /* set if process has used VSX */
0196 #endif /* CONFIG_VSX */
0197 #ifdef CONFIG_SPE
0198     struct_group(spe,
0199         unsigned long   evr[32];    /* upper 32-bits of SPE regs */
0200         u64     acc;        /* Accumulator */
0201     );
0202     unsigned long   spefscr;    /* SPE & eFP status */
0203     unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
0204                        call or trap return */
0205     int     used_spe;   /* set if process has used spe */
0206 #endif /* CONFIG_SPE */
0207 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
0208     u8  load_tm;
0209     u64     tm_tfhar;   /* Transaction fail handler addr */
0210     u64     tm_texasr;  /* Transaction exception & summary */
0211     u64     tm_tfiar;   /* Transaction fail instr address reg */
0212     struct pt_regs  ckpt_regs;  /* Checkpointed registers */
0213 
0214     unsigned long   tm_tar;
0215     unsigned long   tm_ppr;
0216     unsigned long   tm_dscr;
0217     unsigned long   tm_amr;
0218 
0219     /*
0220      * Checkpointed FP and VSX 0-31 register set.
0221      *
0222      * When a transaction is active/signalled/scheduled etc., *regs is the
0223      * most recent set of/speculated GPRs with ckpt_regs being the older
0224      * checkpointed regs to which we roll back if transaction aborts.
0225      *
0226      * These are analogous to how ckpt_regs and pt_regs work
0227      */
0228     struct thread_fp_state ckfp_state; /* Checkpointed FP state */
0229     struct thread_vr_state ckvr_state; /* Checkpointed VR state */
0230     unsigned long   ckvrsave; /* Checkpointed VRSAVE */
0231 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
0232 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
0233     void*       kvm_shadow_vcpu; /* KVM internal data */
0234 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
0235 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
0236     struct kvm_vcpu *kvm_vcpu;
0237 #endif
0238 #ifdef CONFIG_PPC64
0239     unsigned long   dscr;
0240     unsigned long   fscr;
0241     /*
0242      * This member element dscr_inherit indicates that the process
0243      * has explicitly attempted and changed the DSCR register value
0244      * for itself. Hence kernel wont use the default CPU DSCR value
0245      * contained in the PACA structure anymore during process context
0246      * switch. Once this variable is set, this behaviour will also be
0247      * inherited to all the children of this process from that point
0248      * onwards.
0249      */
0250     int     dscr_inherit;
0251     unsigned long   tidr;
0252 #endif
0253 #ifdef CONFIG_PPC_BOOK3S_64
0254     unsigned long   tar;
0255     unsigned long   ebbrr;
0256     unsigned long   ebbhr;
0257     unsigned long   bescr;
0258     unsigned long   siar;
0259     unsigned long   sdar;
0260     unsigned long   sier;
0261     unsigned long   mmcr2;
0262     unsigned    mmcr0;
0263 
0264     unsigned    used_ebb;
0265     unsigned long   mmcr3;
0266     unsigned long   sier2;
0267     unsigned long   sier3;
0268 
0269 #endif
0270 };
0271 
0272 #define ARCH_MIN_TASKALIGN 16
0273 
0274 #define INIT_SP     (sizeof(init_stack) + (unsigned long) &init_stack)
0275 #define INIT_SP_LIMIT   ((unsigned long)&init_stack)
0276 
0277 #ifdef CONFIG_SPE
0278 #define SPEFSCR_INIT \
0279     .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
0280     .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
0281 #else
0282 #define SPEFSCR_INIT
0283 #endif
0284 
0285 #ifdef CONFIG_PPC_BOOK3S_32
0286 #define SR0_INIT    .sr0 = IS_ENABLED(CONFIG_PPC_KUEP) ? SR_NX : 0,
0287 #else
0288 #define SR0_INIT
0289 #endif
0290 
0291 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
0292 #define INIT_THREAD { \
0293     .ksp = INIT_SP, \
0294     .pgdir = swapper_pg_dir, \
0295     .kuap = ~0UL, /* KUAP_NONE */ \
0296     .fpexc_mode = MSR_FE0 | MSR_FE1, \
0297     SPEFSCR_INIT \
0298     SR0_INIT \
0299 }
0300 #elif defined(CONFIG_PPC32)
0301 #define INIT_THREAD { \
0302     .ksp = INIT_SP, \
0303     .pgdir = swapper_pg_dir, \
0304     .fpexc_mode = MSR_FE0 | MSR_FE1, \
0305     SPEFSCR_INIT \
0306     SR0_INIT \
0307 }
0308 #else
0309 #define INIT_THREAD  { \
0310     .ksp = INIT_SP, \
0311     .fpexc_mode = 0, \
0312 }
0313 #endif
0314 
0315 #define task_pt_regs(tsk)   ((tsk)->thread.regs)
0316 
0317 unsigned long __get_wchan(struct task_struct *p);
0318 
0319 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
0320 #define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
0321 
0322 /* Get/set floating-point exception mode */
0323 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
0324 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
0325 
0326 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
0327 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
0328 
0329 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
0330 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
0331 
0332 extern int get_endian(struct task_struct *tsk, unsigned long adr);
0333 extern int set_endian(struct task_struct *tsk, unsigned int val);
0334 
0335 #define GET_UNALIGN_CTL(tsk, adr)   get_unalign_ctl((tsk), (adr))
0336 #define SET_UNALIGN_CTL(tsk, val)   set_unalign_ctl((tsk), (val))
0337 
0338 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
0339 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
0340 
0341 extern void load_fp_state(struct thread_fp_state *fp);
0342 extern void store_fp_state(struct thread_fp_state *fp);
0343 extern void load_vr_state(struct thread_vr_state *vr);
0344 extern void store_vr_state(struct thread_vr_state *vr);
0345 
0346 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
0347 {
0348     return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
0349 }
0350 
0351 static inline unsigned long __pack_fe01(unsigned int fpmode)
0352 {
0353     return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
0354 }
0355 
0356 #ifdef CONFIG_PPC64
0357 
0358 #define spin_begin()    HMT_low()
0359 
0360 #define spin_cpu_relax()    barrier()
0361 
0362 #define spin_end()  HMT_medium()
0363 
0364 #endif
0365 
0366 /* Check that a certain kernel stack pointer is valid in task_struct p */
0367 int validate_sp(unsigned long sp, struct task_struct *p,
0368                        unsigned long nbytes);
0369 
0370 /*
0371  * Prefetch macros.
0372  */
0373 #define ARCH_HAS_PREFETCH
0374 #define ARCH_HAS_PREFETCHW
0375 #define ARCH_HAS_SPINLOCK_PREFETCH
0376 
0377 static inline void prefetch(const void *x)
0378 {
0379     if (unlikely(!x))
0380         return;
0381 
0382     __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
0383 }
0384 
0385 static inline void prefetchw(const void *x)
0386 {
0387     if (unlikely(!x))
0388         return;
0389 
0390     __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
0391 }
0392 
0393 #define spin_lock_prefetch(x)   prefetchw(x)
0394 
0395 /* asm stubs */
0396 extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
0397 extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
0398 extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
0399 #ifdef CONFIG_PPC_970_NAP
0400 extern void power4_idle_nap(void);
0401 void power4_idle_nap_return(void);
0402 #endif
0403 
0404 extern unsigned long cpuidle_disable;
0405 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
0406 
0407 extern int powersave_nap;   /* set if nap mode can be used in idle loop */
0408 
0409 extern void power7_idle_type(unsigned long type);
0410 extern void arch300_idle_type(unsigned long stop_psscr_val,
0411                   unsigned long stop_psscr_mask);
0412 void pnv_power9_force_smt4_catch(void);
0413 void pnv_power9_force_smt4_release(void);
0414 
0415 extern int fix_alignment(struct pt_regs *);
0416 
0417 #ifdef CONFIG_PPC64
0418 /*
0419  * We handle most unaligned accesses in hardware. On the other hand 
0420  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
0421  * powers of 2 writes until it reaches sufficient alignment).
0422  *
0423  * Based on this we disable the IP header alignment in network drivers.
0424  */
0425 #define NET_IP_ALIGN    0
0426 #endif
0427 
0428 int do_mathemu(struct pt_regs *regs);
0429 
0430 /* VMX copying */
0431 int enter_vmx_usercopy(void);
0432 int exit_vmx_usercopy(void);
0433 int enter_vmx_ops(void);
0434 void *exit_vmx_ops(void *dest);
0435 
0436 #endif /* __KERNEL__ */
0437 #endif /* __ASSEMBLY__ */
0438 #endif /* _ASM_POWERPC_PROCESSOR_H */
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