include/asm/pnv-ocxl.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 // Copyright 2017 IBM Corp.
0003 #ifndef _ASM_PNV_OCXL_H
0004 #define _ASM_PNV_OCXL_H
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/pci.h>
0008
0009 #define PNV_OCXL_TL_MAX_TEMPLATE        63
0010 #define PNV_OCXL_TL_BITS_PER_RATE       4
0011 #define PNV_OCXL_TL_RATE_BUF_SIZE       ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
0012
0013 #define PNV_OCXL_ATSD_TIMEOUT       1
0014
0015 /* TLB Management Instructions */
0016 #define PNV_OCXL_ATSD_LNCH      0x00
0017 /* Radix Invalidate */
0018 #define   PNV_OCXL_ATSD_LNCH_R      PPC_BIT(0)
0019 /* Radix Invalidation Control
0020  * 0b00 Just invalidate TLB.
0021  * 0b01 Invalidate just Page Walk Cache.
0022  * 0b10 Invalidate TLB, Page Walk Cache, and any
0023  * caching of Partition and Process Table Entries.
0024  */
0025 #define   PNV_OCXL_ATSD_LNCH_RIC    PPC_BITMASK(1, 2)
0026 /* Number and Page Size of translations to be invalidated */
0027 #define   PNV_OCXL_ATSD_LNCH_LP     PPC_BITMASK(3, 10)
0028 /* Invalidation Criteria
0029  * 0b00 Invalidate just the target VA.
0030  * 0b01 Invalidate matching PID.
0031  */
0032 #define   PNV_OCXL_ATSD_LNCH_IS     PPC_BITMASK(11, 12)
0033 /* 0b1: Process Scope, 0b0: Partition Scope */
0034 #define   PNV_OCXL_ATSD_LNCH_PRS    PPC_BIT(13)
0035 /* Invalidation Flag */
0036 #define   PNV_OCXL_ATSD_LNCH_B      PPC_BIT(14)
0037 /* Actual Page Size to be invalidated
0038  * 000 4KB
0039  * 101 64KB
0040  * 001 2MB
0041  * 010 1GB
0042  */
0043 #define   PNV_OCXL_ATSD_LNCH_AP     PPC_BITMASK(15, 17)
0044 /* Defines the large page select
0045  * L=0b0 for 4KB pages
0046  * L=0b1 for large pages)
0047  */
0048 #define   PNV_OCXL_ATSD_LNCH_L      PPC_BIT(18)
0049 /* Process ID */
0050 #define   PNV_OCXL_ATSD_LNCH_PID    PPC_BITMASK(19, 38)
0051 /* NoFlush – Assumed to be 0b0 */
0052 #define   PNV_OCXL_ATSD_LNCH_F      PPC_BIT(39)
0053 #define   PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40)
0054 #define   PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON    PPC_BIT(41)
0055 #define PNV_OCXL_ATSD_AVA       0x08
0056 #define   PNV_OCXL_ATSD_AVA_AVA     PPC_BITMASK(0, 51)
0057 #define PNV_OCXL_ATSD_STAT      0x10
0058
0059 int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported);
0060 int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
0061
0062 int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
0063             char *rate_buf, int rate_buf_size);
0064 int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
0065              uint64_t rate_buf_phys, int rate_buf_size);
0066
0067 int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
0068 void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
0069                  void __iomem *tfc, void __iomem *pe_handle);
0070 int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
0071               void __iomem **dar, void __iomem **tfc,
0072               void __iomem **pe_handle);
0073
0074 int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data);
0075 void pnv_ocxl_spa_release(void *platform_data);
0076 int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
0077
0078 int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
0079               uint64_t lpcr, void __iomem **arva);
0080 void pnv_ocxl_unmap_lpar(void __iomem *arva);
0081 void pnv_ocxl_tlb_invalidate(void __iomem *arva,
0082                  unsigned long pid,
0083                  unsigned long addr,
0084                  unsigned long page_size);
0085 #endif /* _ASM_PNV_OCXL_H */