include/asm/perf_event_fsl_emb.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Performance event support - Freescale embedded specific definitions.
0004  *
0005  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
0006  * Copyright 2010 Freescale Semiconductor, Inc.
0007  */
0008
0009 #include <linux/types.h>
0010 #include <asm/hw_irq.h>
0011
0012 #define MAX_HWEVENTS 6
0013
0014 /* event flags */
0015 #define FSL_EMB_EVENT_VALID      1
0016 #define FSL_EMB_EVENT_RESTRICTED 2
0017
0018 /* upper half of event flags is PMLCb */
0019 #define FSL_EMB_EVENT_THRESHMUL  0x0000070000000000ULL
0020 #define FSL_EMB_EVENT_THRESH     0x0000003f00000000ULL
0021
0022 struct fsl_emb_pmu {
0023     const char  *name;
0024     int     n_counter; /* total number of counters */
0025
0026     /*
0027      * The number of contiguous counters starting at zero that
0028      * can hold restricted events, or zero if there are no
0029      * restricted events.
0030      *
0031      * This isn't a very flexible method of expressing constraints,
0032      * but it's very simple and is adequate for existing chips.
0033      */
0034     int     n_restricted;
0035
0036     /* Returns event flags and PMLCb (FSL_EMB_EVENT_*) */
0037     u64     (*xlate_event)(u64 event_id);
0038
0039     int     n_generic;
0040     int     *generic_events;
0041     int     (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
0042                    [PERF_COUNT_HW_CACHE_OP_MAX]
0043                    [PERF_COUNT_HW_CACHE_RESULT_MAX];
0044 };
0045
0046 int register_fsl_emb_pmu(struct fsl_emb_pmu *);