include/asm/perf_event.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Performance event support - hardware-specific disambiguation
0004  *
0005  * For now this is a compile-time decision, but eventually it should be
0006  * runtime.  This would allow multiplatform perf event support for e300 (fsl
0007  * embedded perf counters) plus server/classic, and would accommodate
0008  * devices other than the core which provide their own performance counters.
0009  *
0010  * Copyright 2010 Freescale Semiconductor, Inc.
0011  */
0012
0013 #ifdef CONFIG_PPC_PERF_CTRS
0014 #include <asm/perf_event_server.h>
0015 #else
0016 static inline bool is_sier_available(void) { return false; }
0017 static inline unsigned long get_pmcs_ext_regs(int idx) { return 0; }
0018 #endif
0019
0020 #ifdef CONFIG_FSL_EMB_PERF_EVENT
0021 #include <asm/perf_event_fsl_emb.h>
0022 #endif
0023
0024 #ifdef CONFIG_PERF_EVENTS
0025 #include <asm/ptrace.h>
0026 #include <asm/reg.h>
0027
0028 #define perf_arch_bpf_user_pt_regs(regs) &regs->user_regs
0029
0030 /*
0031  * Overload regs->result to specify whether we should use the MSR (result
0032  * is zero) or the SIAR (result is non zero).
0033  */
0034 #define perf_arch_fetch_caller_regs(regs, __ip)         \
0035     do {                            \
0036         (regs)->result = 0;             \
0037         (regs)->nip = __ip;             \
0038         (regs)->gpr[1] = current_stack_frame();     \
0039         asm volatile("mfmsr %0" : "=r" ((regs)->msr));  \
0040     } while (0)
0041
0042 /* To support perf_regs sier update */
0043 extern bool is_sier_available(void);
0044 extern unsigned long get_pmcs_ext_regs(int idx);
0045 /* To define perf extended regs mask value */
0046 extern u64 PERF_REG_EXTENDED_MASK;
0047 #define PERF_REG_EXTENDED_MASK  PERF_REG_EXTENDED_MASK
0048 #endif