include/asm/pci-bridge.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
0003 #define _ASM_POWERPC_PCI_BRIDGE_H
0004 #ifdef __KERNEL__
0005 /*
0006  */
0007 #include <linux/pci.h>
0008 #include <linux/list.h>
0009 #include <linux/ioport.h>
0010 #include <linux/numa.h>
0011
0012 struct device_node;
0013
0014 /*
0015  * PCI controller operations
0016  */
0017 struct pci_controller_ops {
0018     void        (*dma_dev_setup)(struct pci_dev *pdev);
0019     void        (*dma_bus_setup)(struct pci_bus *bus);
0020     bool        (*iommu_bypass_supported)(struct pci_dev *pdev,
0021                 u64 mask);
0022
0023     int     (*probe_mode)(struct pci_bus *bus);
0024
0025     /* Called when pci_enable_device() is called. Returns true to
0026      * allow assignment/enabling of the device. */
0027     bool        (*enable_device_hook)(struct pci_dev *pdev);
0028
0029     void        (*disable_device)(struct pci_dev *pdev);
0030
0031     void        (*release_device)(struct pci_dev *pdev);
0032
0033     /* Called during PCI resource reassignment */
0034     resource_size_t (*window_alignment)(struct pci_bus *bus,
0035                         unsigned long type);
0036     void        (*setup_bridge)(struct pci_bus *bus,
0037                     unsigned long type);
0038     void        (*reset_secondary_bus)(struct pci_dev *pdev);
0039
0040 #ifdef CONFIG_PCI_MSI
0041     int     (*setup_msi_irqs)(struct pci_dev *pdev,
0042                       int nvec, int type);
0043     void        (*teardown_msi_irqs)(struct pci_dev *pdev);
0044 #endif
0045
0046     void        (*shutdown)(struct pci_controller *hose);
0047 };
0048
0049 /*
0050  * Structure of a PCI controller (host bridge)
0051  */
0052 struct pci_controller {
0053     struct pci_bus *bus;
0054     char is_dynamic;
0055 #ifdef CONFIG_PPC64
0056     int node;
0057 #endif
0058     struct device_node *dn;
0059     struct list_head list_node;
0060     struct device *parent;
0061
0062     int first_busno;
0063     int last_busno;
0064     int self_busno;
0065     struct resource busn;
0066
0067     void __iomem *io_base_virt;
0068 #ifdef CONFIG_PPC64
0069     void __iomem *io_base_alloc;
0070 #endif
0071     resource_size_t io_base_phys;
0072     resource_size_t pci_io_size;
0073
0074     /* Some machines have a special region to forward the ISA
0075      * "memory" cycles such as VGA memory regions. Left to 0
0076      * if unsupported
0077      */
0078     resource_size_t isa_mem_phys;
0079     resource_size_t isa_mem_size;
0080
0081     struct pci_controller_ops controller_ops;
0082     struct pci_ops *ops;
0083     unsigned int __iomem *cfg_addr;
0084     void __iomem *cfg_data;
0085
0086     /*
0087      * Used for variants of PCI indirect handling and possible quirks:
0088      *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
0089      *  EXT_REG - provides access to PCI-e extended registers
0090      *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
0091      *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
0092      *   to determine which bus number to match on when generating type0
0093      *   config cycles
0094      *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
0095      *   hanging if we don't have link and try to do config cycles to
0096      *   anything but the PHB.  Only allow talking to the PHB if this is
0097      *   set.
0098      *  BIG_ENDIAN - cfg_addr is a big endian register
0099      *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
0100      *   the PLB4.  Effectively disable MRM commands by setting this.
0101      *  FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
0102      *   link status is in a RC PCIe cfg register (vs being a SoC register)
0103      */
0104 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE      0x00000001
0105 #define PPC_INDIRECT_TYPE_EXT_REG       0x00000002
0106 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS  0x00000004
0107 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK      0x00000008
0108 #define PPC_INDIRECT_TYPE_BIG_ENDIAN        0x00000010
0109 #define PPC_INDIRECT_TYPE_BROKEN_MRM        0x00000020
0110 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK  0x00000040
0111     u32 indirect_type;
0112     /* Currently, we limit ourselves to 1 IO range and 3 mem
0113      * ranges since the common pci_bus structure can't handle more
0114      */
0115     struct resource io_resource;
0116     struct resource mem_resources[3];
0117     resource_size_t mem_offset[3];
0118     int global_number;      /* PCI domain number */
0119
0120     resource_size_t dma_window_base_cur;
0121     resource_size_t dma_window_size;
0122
0123 #ifdef CONFIG_PPC64
0124     unsigned long buid;
0125     struct pci_dn *pci_data;
0126 #endif  /* CONFIG_PPC64 */
0127
0128     void *private_data;
0129
0130     /* IRQ domain hierarchy */
0131     struct irq_domain   *dev_domain;
0132     struct irq_domain   *msi_domain;
0133     struct fwnode_handle    *fwnode;
0134 };
0135
0136 /* These are used for config access before all the PCI probing
0137    has been done. */
0138 extern int early_read_config_byte(struct pci_controller *hose, int bus,
0139             int dev_fn, int where, u8 *val);
0140 extern int early_read_config_word(struct pci_controller *hose, int bus,
0141             int dev_fn, int where, u16 *val);
0142 extern int early_read_config_dword(struct pci_controller *hose, int bus,
0143             int dev_fn, int where, u32 *val);
0144 extern int early_write_config_byte(struct pci_controller *hose, int bus,
0145             int dev_fn, int where, u8 val);
0146 extern int early_write_config_word(struct pci_controller *hose, int bus,
0147             int dev_fn, int where, u16 val);
0148 extern int early_write_config_dword(struct pci_controller *hose, int bus,
0149             int dev_fn, int where, u32 val);
0150
0151 extern int early_find_capability(struct pci_controller *hose, int bus,
0152                  int dev_fn, int cap);
0153
0154 extern void setup_indirect_pci(struct pci_controller* hose,
0155                    resource_size_t cfg_addr,
0156                    resource_size_t cfg_data, u32 flags);
0157
0158 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
0159                 int offset, int len, u32 *val);
0160
0161 extern int __indirect_read_config(struct pci_controller *hose,
0162                   unsigned char bus_number, unsigned int devfn,
0163                   int offset, int len, u32 *val);
0164
0165 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
0166                  int offset, int len, u32 val);
0167
0168 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
0169 {
0170     return bus->sysdata;
0171 }
0172
0173 #ifdef CONFIG_PPC_PMAC
0174 extern int pci_device_from_OF_node(struct device_node *node,
0175                    u8 *bus, u8 *devfn);
0176 #endif
0177 #ifndef CONFIG_PPC64
0178
0179 #ifdef CONFIG_PPC_CHRP
0180 extern void pci_create_OF_bus_map(void);
0181 #endif
0182
0183 #else   /* CONFIG_PPC64 */
0184
0185 /*
0186  * PCI stuff, for nodes representing PCI devices, pointed to
0187  * by device_node->data.
0188  */
0189 struct iommu_table;
0190
0191 struct pci_dn {
0192     int     flags;
0193 #define PCI_DN_FLAG_IOV_VF  0x01
0194 #define PCI_DN_FLAG_DEAD    0x02    /* Device has been hot-removed */
0195
0196     int busno;          /* pci bus number */
0197     int devfn;          /* pci device and function number */
0198     int vendor_id;      /* Vendor ID */
0199     int device_id;      /* Device ID */
0200     int class_code;     /* Device class code */
0201
0202     struct  pci_dn *parent;
0203     struct  pci_controller *phb;    /* for pci devices */
0204     struct  iommu_table_group *table_group; /* for phb's or bridges */
0205
0206     int pci_ext_config_space;   /* for pci devices */
0207 #ifdef CONFIG_EEH
0208     struct eeh_dev *edev;       /* eeh device */
0209 #endif
0210 #define IODA_INVALID_PE     0xFFFFFFFF
0211     unsigned int pe_number;
0212 #ifdef CONFIG_PCI_IOV
0213     u16     vfs_expanded;       /* number of VFs IOV BAR expanded */
0214     u16     num_vfs;        /* number of VFs enabled*/
0215     unsigned int *pe_num_map;   /* PE# for the first VF PE or array */
0216     bool    m64_single_mode;    /* Use M64 BAR in Single Mode */
0217 #define IODA_INVALID_M64        (-1)
0218     int     (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
0219     int     last_allow_rc;          /* Only used on pseries */
0220 #endif /* CONFIG_PCI_IOV */
0221     int mps;            /* Maximum Payload Size */
0222     struct list_head child_list;
0223     struct list_head list;
0224     struct resource holes[PCI_SRIOV_NUM_BARS];
0225 };
0226
0227 /* Get the pointer to a device_node's pci_dn */
0228 #define PCI_DN(dn)  ((struct pci_dn *) (dn)->data)
0229
0230 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
0231                        int devfn);
0232 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
0233 extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
0234                            struct device_node *dn);
0235 extern void pci_remove_device_node_info(struct device_node *dn);
0236
0237 #ifdef CONFIG_PCI_IOV
0238 struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
0239 void remove_sriov_vf_pdns(struct pci_dev *pdev);
0240 #endif
0241
0242 #if defined(CONFIG_EEH)
0243 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
0244 {
0245     return pdn ? pdn->edev : NULL;
0246 }
0247 #else
0248 #define pdn_to_eeh_dev(x)   (NULL)
0249 #endif
0250
0251 /** Find the bus corresponding to the indicated device node */
0252 extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
0253
0254 /** Remove all of the PCI devices under this bus */
0255 extern void pci_hp_remove_devices(struct pci_bus *bus);
0256
0257 /** Discover new pci devices under this bus, and add them */
0258 extern void pci_hp_add_devices(struct pci_bus *bus);
0259
0260 extern int pcibios_unmap_io_space(struct pci_bus *bus);
0261 extern int pcibios_map_io_space(struct pci_bus *bus);
0262
0263 #ifdef CONFIG_NUMA
0264 #define PHB_SET_NODE(PHB, NODE)     ((PHB)->node = (NODE))
0265 #else
0266 #define PHB_SET_NODE(PHB, NODE)     ((PHB)->node = NUMA_NO_NODE)
0267 #endif
0268
0269 #endif  /* CONFIG_PPC64 */
0270
0271 /* Get the PCI host controller for an OF device */
0272 extern struct pci_controller *pci_find_hose_for_OF_device(
0273             struct device_node* node);
0274
0275 extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
0276
0277 /* Fill up host controller resources from the OF node */
0278 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
0279             struct device_node *dev, int primary);
0280
0281 /* Allocate & free a PCI host bridge structure */
0282 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
0283 extern void pcibios_free_controller(struct pci_controller *phb);
0284 extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
0285
0286 #ifdef CONFIG_PCI
0287 extern int pcibios_vaddr_is_ioport(void __iomem *address);
0288 #else
0289 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
0290 {
0291     return 0;
0292 }
0293 #endif  /* CONFIG_PCI */
0294
0295 #endif  /* __KERNEL__ */
0296 #endif  /* _ASM_POWERPC_PCI_BRIDGE_H */