include/asm/page_32.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_PAGE_32_H
0003 #define _ASM_POWERPC_PAGE_32_H
0004
0005 #include <asm/cache.h>
0006
0007 #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
0008 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
0009 #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
0010 #endif
0011 #endif
0012
0013 #define VM_DATA_DEFAULT_FLAGS   VM_DATA_DEFAULT_FLAGS32
0014
0015 #ifdef CONFIG_NOT_COHERENT_CACHE
0016 #define ARCH_DMA_MINALIGN   L1_CACHE_BYTES
0017 #endif
0018
0019 #if defined(CONFIG_PPC_256K_PAGES) || \
0020     (defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES))
0021 #define PTE_SHIFT   (PAGE_SHIFT - PTE_T_LOG2 - 2)   /* 1/4 of a page */
0022 #else
0023 #define PTE_SHIFT   (PAGE_SHIFT - PTE_T_LOG2)   /* full page */
0024 #endif
0025
0026 #ifndef __ASSEMBLY__
0027 /*
0028  * The basic type of a PTE - 64 bits for those CPUs with > 32 bit
0029  * physical addressing.
0030  */
0031 #ifdef CONFIG_PTE_64BIT
0032 typedef unsigned long long pte_basic_t;
0033 #else
0034 typedef unsigned long pte_basic_t;
0035 #endif
0036
0037 #include <asm/bug.h>
0038
0039 /*
0040  * Clear page using the dcbz instruction, which doesn't cause any
0041  * memory traffic (except to write out any cache lines which get
0042  * displaced).  This only works on cacheable memory.
0043  */
0044 static inline void clear_page(void *addr)
0045 {
0046     unsigned int i;
0047
0048     WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));
0049
0050     for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
0051         dcbz(addr);
0052 }
0053 extern void copy_page(void *to, void *from);
0054
0055 #include <asm-generic/getorder.h>
0056
0057 #define PGD_T_LOG2  (__builtin_ffs(sizeof(pgd_t)) - 1)
0058 #define PTE_T_LOG2  (__builtin_ffs(sizeof(pte_t)) - 1)
0059
0060 #endif /* __ASSEMBLY__ */
0061
0062 #endif /* _ASM_POWERPC_PAGE_32_H */