include/asm/paca.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * This control block defines the PACA which defines the processor
0004  * specific data for each logical processor on the system.
0005  * There are some pointers defined that are utilized by PLIC.
0006  *
0007  * C 2001 PPC 64 Team, IBM Corp
0008  */
0009 #ifndef _ASM_POWERPC_PACA_H
0010 #define _ASM_POWERPC_PACA_H
0011 #ifdef __KERNEL__
0012
0013 #ifdef CONFIG_PPC64
0014
0015 #include <linux/cache.h>
0016 #include <linux/string.h>
0017 #include <asm/types.h>
0018 #include <asm/lppaca.h>
0019 #include <asm/mmu.h>
0020 #include <asm/page.h>
0021 #ifdef CONFIG_PPC_BOOK3E
0022 #include <asm/exception-64e.h>
0023 #else
0024 #include <asm/exception-64s.h>
0025 #endif
0026 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
0027 #include <asm/kvm_book3s_asm.h>
0028 #endif
0029 #include <asm/accounting.h>
0030 #include <asm/hmi.h>
0031 #include <asm/cpuidle.h>
0032 #include <asm/atomic.h>
0033 #include <asm/mce.h>
0034
0035 #include <asm-generic/mmiowb_types.h>
0036
0037 register struct paca_struct *local_paca asm("r13");
0038
0039 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
0040 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
0041 /*
0042  * Add standard checks that preemption cannot occur when using get_paca():
0043  * otherwise the paca_struct it points to may be the wrong one just after.
0044  */
0045 #define get_paca()  ((void) debug_smp_processor_id(), local_paca)
0046 #else
0047 #define get_paca()  local_paca
0048 #endif
0049
0050 #ifdef CONFIG_PPC_PSERIES
0051 #define get_lppaca()    (get_paca()->lppaca_ptr)
0052 #endif
0053
0054 #define get_slb_shadow()    (get_paca()->slb_shadow_ptr)
0055
0056 struct task_struct;
0057 struct rtas_args;
0058
0059 /*
0060  * Defines the layout of the paca.
0061  *
0062  * This structure is not directly accessed by firmware or the service
0063  * processor.
0064  */
0065 struct paca_struct {
0066 #ifdef CONFIG_PPC_PSERIES
0067     /*
0068      * Because hw_cpu_id, unlike other paca fields, is accessed
0069      * routinely from other CPUs (from the IRQ code), we stick to
0070      * read-only (after boot) fields in the first cacheline to
0071      * avoid cacheline bouncing.
0072      */
0073
0074     struct lppaca *lppaca_ptr;  /* Pointer to LpPaca for PLIC */
0075 #endif /* CONFIG_PPC_PSERIES */
0076
0077     /*
0078      * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
0079      * load lock_token and paca_index with a single lwz
0080      * instruction.  They must travel together and be properly
0081      * aligned.
0082      */
0083 #ifdef __BIG_ENDIAN__
0084     u16 lock_token;         /* Constant 0x8000, used in locks */
0085     u16 paca_index;         /* Logical processor number */
0086 #else
0087     u16 paca_index;         /* Logical processor number */
0088     u16 lock_token;         /* Constant 0x8000, used in locks */
0089 #endif
0090
0091     u64 kernel_toc;         /* Kernel TOC address */
0092     u64 kernelbase;         /* Base address of kernel */
0093     u64 kernel_msr;         /* MSR while running in kernel */
0094     void *emergency_sp;     /* pointer to emergency stack */
0095     u64 data_offset;        /* per cpu data offset */
0096     s16 hw_cpu_id;          /* Physical processor number */
0097     u8 cpu_start;           /* At startup, processor spins until */
0098                     /* this becomes non-zero. */
0099     u8 kexec_state;     /* set when kexec down has irqs off */
0100 #ifdef CONFIG_PPC_BOOK3S_64
0101 #ifdef CONFIG_PPC_64S_HASH_MMU
0102     struct slb_shadow *slb_shadow_ptr;
0103 #endif
0104     struct dtl_entry *dispatch_log;
0105     struct dtl_entry *dispatch_log_end;
0106 #endif
0107     u64 dscr_default;       /* per-CPU default DSCR */
0108
0109 #ifdef CONFIG_PPC_BOOK3S_64
0110     /*
0111      * Now, starting in cacheline 2, the exception save areas
0112      */
0113     /* used for most interrupts/exceptions */
0114     u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
0115
0116 #ifdef CONFIG_PPC_64S_HASH_MMU
0117     /* SLB related definitions */
0118     u16 vmalloc_sllp;
0119     u8 slb_cache_ptr;
0120     u8 stab_rr;         /* stab/slb round-robin counter */
0121 #ifdef CONFIG_DEBUG_VM
0122     u8 in_kernel_slb_handler;
0123 #endif
0124     u32 slb_used_bitmap;        /* Bitmaps for first 32 SLB entries. */
0125     u32 slb_kern_bitmap;
0126     u32 slb_cache[SLB_CACHE_ENTRIES];
0127 #endif
0128 #endif /* CONFIG_PPC_BOOK3S_64 */
0129
0130 #ifdef CONFIG_PPC_BOOK3E
0131     u64 exgen[8] __aligned(0x40);
0132     /* Keep pgd in the same cacheline as the start of extlb */
0133     pgd_t *pgd __aligned(0x40); /* Current PGD */
0134     pgd_t *kernel_pgd;      /* Kernel PGD */
0135
0136     /* Shared by all threads of a core -- points to tcd of first thread */
0137     struct tlb_core_data *tcd_ptr;
0138
0139     /*
0140      * We can have up to 3 levels of reentrancy in the TLB miss handler,
0141      * in each of four exception levels (normal, crit, mcheck, debug).
0142      */
0143     u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
0144     u64 exmc[8];        /* used for machine checks */
0145     u64 excrit[8];      /* used for crit interrupts */
0146     u64 exdbg[8];       /* used for debug interrupts */
0147
0148     /* Kernel stack pointers for use by special exceptions */
0149     void *mc_kstack;
0150     void *crit_kstack;
0151     void *dbg_kstack;
0152
0153     struct tlb_core_data tcd;
0154 #endif /* CONFIG_PPC_BOOK3E */
0155
0156 #ifdef CONFIG_PPC_64S_HASH_MMU
0157     unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
0158     unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
0159 #endif
0160
0161     /*
0162      * then miscellaneous read-write fields
0163      */
0164     struct task_struct *__current;  /* Pointer to current */
0165     u64 kstack;         /* Saved Kernel stack addr */
0166     u64 saved_r1;           /* r1 save for RTAS calls or PM or EE=0 */
0167     u64 saved_msr;          /* MSR saved here by enter_rtas */
0168 #ifdef CONFIG_PPC64
0169     u64 exit_save_r1;       /* Syscall/interrupt R1 save */
0170 #endif
0171 #ifdef CONFIG_PPC_BOOK3E
0172     u16 trap_save;          /* Used when bad stack is encountered */
0173 #endif
0174 #ifdef CONFIG_PPC_BOOK3S_64
0175     u8 hsrr_valid;          /* HSRRs set for HRFID */
0176     u8 srr_valid;           /* SRRs set for RFID */
0177 #endif
0178     u8 irq_soft_mask;       /* mask for irq soft masking */
0179     u8 irq_happened;        /* irq happened while soft-disabled */
0180     u8 irq_work_pending;        /* IRQ_WORK interrupt while soft-disable */
0181 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0182     u8 pmcregs_in_use;      /* pseries puts this in lppaca */
0183 #endif
0184     u64 sprg_vdso;          /* Saved user-visible sprg */
0185 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
0186     u64 tm_scratch;                 /* TM scratch area for reclaim */
0187 #endif
0188
0189 #ifdef CONFIG_PPC_POWERNV
0190     /* PowerNV idle fields */
0191     /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
0192     unsigned long idle_state;
0193     union {
0194         /* P7/P8 specific fields */
0195         struct {
0196             /* PNV_THREAD_RUNNING/NAP/SLEEP */
0197             u8 thread_idle_state;
0198             /* Mask to denote subcore sibling threads */
0199             u8 subcore_sibling_mask;
0200         };
0201
0202         /* P9 specific fields */
0203         struct {
0204 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0205             /* The PSSCR value that the kernel requested before going to stop */
0206             u64 requested_psscr;
0207             /* Flag to request this thread not to stop */
0208             atomic_t dont_stop;
0209 #endif
0210         };
0211     };
0212 #endif
0213
0214 #ifdef CONFIG_PPC_BOOK3S_64
0215     /* Non-maskable exceptions that are not performance critical */
0216     u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
0217     u64 exmc[EX_SIZE];  /* used for machine checks */
0218 #endif
0219 #ifdef CONFIG_PPC_BOOK3S_64
0220     /* Exclusive stacks for system reset and machine check exception. */
0221     void *nmi_emergency_sp;
0222     void *mc_emergency_sp;
0223
0224     u16 in_nmi;         /* In nmi handler */
0225
0226     /*
0227      * Flag to check whether we are in machine check early handler
0228      * and already using emergency stack.
0229      */
0230     u16 in_mce;
0231     u8 hmi_event_available;     /* HMI event is available */
0232     u8 hmi_p9_special_emu;      /* HMI P9 special emulation */
0233     u32 hmi_irqs;           /* HMI irq stat */
0234 #endif
0235     u8 ftrace_enabled;      /* Hard disable ftrace */
0236
0237     /* Stuff for accurate time accounting */
0238     struct cpu_accounting_data accounting;
0239     u64 dtl_ridx;           /* read index in dispatch log */
0240     struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
0241
0242 #ifdef CONFIG_KVM_BOOK3S_HANDLER
0243 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
0244     /* We use this to store guest state in */
0245     struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
0246 #endif
0247     struct kvmppc_host_state kvm_hstate;
0248 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0249     /*
0250      * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
0251      * more details
0252      */
0253     struct sibling_subcore_state *sibling_subcore_state;
0254 #endif
0255 #endif
0256 #ifdef CONFIG_PPC_BOOK3S_64
0257     /*
0258      * rfi fallback flush must be in its own cacheline to prevent
0259      * other paca data leaking into the L1d
0260      */
0261     u64 exrfi[EX_SIZE] __aligned(0x80);
0262     void *rfi_flush_fallback_area;
0263     u64 l1d_flush_size;
0264 #endif
0265 #ifdef CONFIG_PPC_PSERIES
0266     struct rtas_args *rtas_args_reentrant;
0267     u8 *mce_data_buf;       /* buffer to hold per cpu rtas errlog */
0268 #endif /* CONFIG_PPC_PSERIES */
0269
0270 #ifdef CONFIG_PPC_BOOK3S_64
0271 #ifdef CONFIG_PPC_64S_HASH_MMU
0272     /* Capture SLB related old contents in MCE handler. */
0273     struct slb_entry *mce_faulty_slbs;
0274     u16 slb_save_cache_ptr;
0275 #endif
0276 #endif /* CONFIG_PPC_BOOK3S_64 */
0277 #ifdef CONFIG_STACKPROTECTOR
0278     unsigned long canary;
0279 #endif
0280 #ifdef CONFIG_MMIOWB
0281     struct mmiowb_state mmiowb_state;
0282 #endif
0283 #ifdef CONFIG_PPC_BOOK3S_64
0284     struct mce_info *mce_info;
0285     u8 mce_pending_irq_work;
0286 #endif /* CONFIG_PPC_BOOK3S_64 */
0287 } ____cacheline_aligned;
0288
0289 extern void copy_mm_to_paca(struct mm_struct *mm);
0290 extern struct paca_struct **paca_ptrs;
0291 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
0292 extern void setup_paca(struct paca_struct *new_paca);
0293 extern void allocate_paca_ptrs(void);
0294 extern void allocate_paca(int cpu);
0295 extern void free_unused_pacas(void);
0296
0297 #else /* CONFIG_PPC64 */
0298
0299 static inline void allocate_paca_ptrs(void) { }
0300 static inline void allocate_paca(int cpu) { }
0301 static inline void free_unused_pacas(void) { }
0302
0303 #endif /* CONFIG_PPC64 */
0304
0305 #endif /* __KERNEL__ */
0306 #endif /* _ASM_POWERPC_PACA_H */