include/asm/opal.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * PowerNV OPAL definitions.
0004  *
0005  * Copyright 2011 IBM Corp.
0006  */
0007
0008 #ifndef _ASM_POWERPC_OPAL_H
0009 #define _ASM_POWERPC_OPAL_H
0010
0011 #include <asm/opal-api.h>
0012
0013 #ifndef __ASSEMBLY__
0014
0015 #include <linux/notifier.h>
0016
0017 /* We calculate number of sg entries based on PAGE_SIZE */
0018 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
0019
0020 /* Default time to sleep or delay between OPAL_BUSY/OPAL_BUSY_EVENT loops */
0021 #define OPAL_BUSY_DELAY_MS  10
0022
0023 /* /sys/firmware/opal */
0024 extern struct kobject *opal_kobj;
0025
0026 /* /ibm,opal */
0027 extern struct device_node *opal_node;
0028
0029 /* API functions */
0030 int64_t opal_invalid_call(void);
0031 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
0032             uint64_t lpcr);
0033 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn,
0034             uint64_t addr, uint64_t PE_mask);
0035 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn,
0036                 uint64_t PE_handle);
0037 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap,
0038             uint64_t rate_phys, uint32_t size);
0039
0040 int64_t opal_console_write(int64_t term_number, __be64 *length,
0041                const uint8_t *buffer);
0042 int64_t opal_console_read(int64_t term_number, __be64 *length,
0043               uint8_t *buffer);
0044 int64_t opal_console_write_buffer_space(int64_t term_number,
0045                     __be64 *length);
0046 int64_t opal_console_flush(int64_t term_number);
0047 int64_t opal_rtc_read(__be32 *year_month_day,
0048               __be64 *hour_minute_second_millisecond);
0049 int64_t opal_rtc_write(uint32_t year_month_day,
0050                uint64_t hour_minute_second_millisecond);
0051 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
0052 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
0053                uint32_t hour_min);
0054 int64_t opal_cec_power_down(uint64_t request);
0055 int64_t opal_cec_reboot(void);
0056 int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
0057 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
0058 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
0059 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
0060 int64_t opal_poll_events(__be64 *outstanding_event_mask);
0061 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
0062                     uint64_t tce_mem_size);
0063 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
0064                     uint64_t tce_mem_size);
0065 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
0066                   uint64_t offset, uint8_t *data);
0067 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
0068                        uint64_t offset, __be16 *data);
0069 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
0070                   uint64_t offset, __be32 *data);
0071 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
0072                    uint64_t offset, uint8_t data);
0073 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
0074                     uint64_t offset, uint16_t data);
0075 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
0076                    uint64_t offset, uint32_t data);
0077 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
0078 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
0079 int64_t opal_register_exception_handler(uint64_t opal_exception,
0080                     uint64_t handler_address,
0081                     uint64_t glue_cache_line);
0082 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
0083                    uint8_t *freeze_state,
0084                    __be16 *pci_error_type,
0085                    __be64 *phb_status);
0086 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
0087                   uint64_t eeh_action_token);
0088 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
0089                 uint64_t eeh_action_token);
0090 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
0091                 uint32_t func, uint64_t addr, uint64_t mask);
0092 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
0093
0094
0095
0096 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
0097                  uint16_t window_num, uint16_t enable);
0098 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
0099                     uint16_t window_num,
0100                     uint64_t starting_real_address,
0101                     uint64_t starting_pci_address,
0102                     uint64_t size);
0103 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
0104                     uint16_t window_type, uint16_t window_num,
0105                     uint16_t segment_num);
0106 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
0107                       uint64_t ivt_addr, uint64_t ivt_len,
0108                       uint64_t reject_array_addr,
0109                       uint64_t peltv_addr);
0110 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
0111             uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
0112             uint8_t pe_action);
0113 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
0114                uint8_t state);
0115 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
0116 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
0117                 uint32_t state);
0118 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
0119                   uint8_t *p_bit, uint8_t *q_bit);
0120 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
0121                   uint8_t p_bit, uint8_t q_bit);
0122 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
0123 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
0124                  uint32_t xive_num);
0125 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
0126                  __be32 *interrupt_source_number);
0127 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
0128             uint8_t msi_range, __be32 *msi_address,
0129             __be32 *message_data);
0130 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
0131             uint32_t xive_num, uint8_t msi_range,
0132             __be64 *msi_address, __be32 *message_data);
0133 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
0134 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
0135 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
0136 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
0137                    uint16_t tce_levels, uint64_t tce_table_addr,
0138                    uint64_t tce_table_size, uint64_t tce_page_size);
0139 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
0140                     uint16_t dma_window_number, uint64_t pci_start_addr,
0141                     uint64_t pci_mem_size);
0142 int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
0143
0144 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
0145                    uint64_t diag_buffer_len);
0146 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
0147                    uint64_t diag_buffer_len);
0148 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
0149                     uint64_t diag_buffer_len);
0150 int64_t opal_pci_fence_phb(uint64_t phb_id);
0151 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
0152 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
0153 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
0154 int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
0155 int64_t opal_get_dpo_status(__be64 *dpo_timeout);
0156 int64_t opal_set_system_attention_led(uint8_t led_action);
0157 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
0158                 __be16 *pci_error_type, __be16 *severity);
0159 int64_t opal_pci_poll(uint64_t id);
0160 int64_t opal_return_cpu(void);
0161 int64_t opal_check_token(uint64_t token);
0162 int64_t opal_reinit_cpus(uint64_t flags);
0163
0164 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
0165 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
0166
0167 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
0168                uint32_t addr, uint32_t data, uint32_t sz);
0169 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
0170               uint32_t addr, __be32 *data, uint32_t sz);
0171
0172 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
0173 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
0174 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
0175 int64_t opal_send_ack_elog(uint64_t log_id);
0176 void opal_resend_pending_logs(void);
0177
0178 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
0179 int64_t opal_manage_flash(uint8_t op);
0180 int64_t opal_update_flash(uint64_t blk_list);
0181 int64_t opal_dump_init(uint8_t dump_type);
0182 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
0183 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
0184 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
0185 int64_t opal_dump_ack(uint32_t dump_id);
0186 int64_t opal_dump_resend_notification(void);
0187
0188 int64_t opal_get_msg(uint64_t buffer, uint64_t size);
0189 int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
0190                     uint64_t num_lines);
0191 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
0192 int64_t opal_sync_host_reboot(void);
0193 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
0194         uint64_t length);
0195 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
0196         uint64_t length);
0197 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
0198 int64_t opal_sensor_read_u64(u32 sensor_hndl, int token, __be64 *sensor_data);
0199 int64_t opal_handle_hmi(void);
0200 int64_t opal_handle_hmi2(__be64 *out_flags);
0201 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
0202 int64_t opal_unregister_dump_region(uint32_t id);
0203 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
0204 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
0205 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
0206 int64_t opal_pci_get_pbcq_tunnel_bar(uint64_t phb_id, uint64_t *addr);
0207 int64_t opal_pci_set_pbcq_tunnel_bar(uint64_t phb_id, uint64_t addr);
0208 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
0209         uint64_t msg_len);
0210 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
0211         uint64_t *msg_len);
0212 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
0213              struct opal_i2c_request *oreq);
0214 int64_t opal_prd_msg(struct opal_prd_msg *msg);
0215 int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
0216               __be64 *led_value, __be64 *max_led_type);
0217 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
0218               const u64 led_value, __be64 *max_led_type);
0219
0220 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
0221         uint64_t size, uint64_t token);
0222 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
0223         uint64_t size, uint64_t token);
0224 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
0225         uint64_t token);
0226 int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
0227 int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
0228 int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
0229 int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
0230                  uint64_t data);
0231 int64_t opal_pci_poll2(uint64_t id, uint64_t data);
0232
0233 int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
0234 int64_t opal_int_set_cppr(uint8_t cppr);
0235 int64_t opal_int_eoi(uint32_t xirr);
0236 int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
0237 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
0238               uint32_t pe_num, uint32_t tce_size,
0239               uint64_t dma_addr, uint32_t npages);
0240 int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
0241 int64_t opal_xive_reset(uint64_t version);
0242 int64_t opal_xive_get_irq_info(uint32_t girq,
0243                    __be64 *out_flags,
0244                    __be64 *out_eoi_page,
0245                    __be64 *out_trig_page,
0246                    __be32 *out_esb_shift,
0247                    __be32 *out_src_chip);
0248 int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
0249                  uint8_t *out_prio, __be32 *out_lirq);
0250 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
0251                  uint32_t lirq);
0252 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
0253                  __be64 *out_qpage,
0254                  __be64 *out_qsize,
0255                  __be64 *out_qeoi_page,
0256                  __be32 *out_escalate_irq,
0257                  __be64 *out_qflags);
0258 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
0259                  uint64_t qpage,
0260                  uint64_t qsize,
0261                  uint64_t qflags);
0262 int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
0263 int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
0264 int64_t opal_xive_free_vp_block(uint64_t vp);
0265 int64_t opal_xive_get_vp_info(uint64_t vp,
0266                   __be64 *out_flags,
0267                   __be64 *out_cam_value,
0268                   __be64 *out_report_cl_pair,
0269                   __be32 *out_chip_id);
0270 int64_t opal_xive_set_vp_info(uint64_t vp,
0271                   uint64_t flags,
0272                   uint64_t report_cl_pair);
0273 int64_t opal_xive_allocate_irq_raw(uint32_t chip_id);
0274 int64_t opal_xive_free_irq(uint32_t girq);
0275 int64_t opal_xive_sync(uint32_t type, uint32_t id);
0276 int64_t opal_xive_dump(uint32_t type, uint32_t id);
0277 int64_t opal_xive_get_queue_state(uint64_t vp, uint32_t prio,
0278                   __be32 *out_qtoggle,
0279                   __be32 *out_qindex);
0280 int64_t opal_xive_set_queue_state(uint64_t vp, uint32_t prio,
0281                   uint32_t qtoggle,
0282                   uint32_t qindex);
0283 int64_t opal_xive_get_vp_state(uint64_t vp, __be64 *out_w01);
0284
0285 int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
0286                             uint64_t cpu_pir);
0287 int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
0288 int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
0289
0290 int opal_get_powercap(u32 handle, int token, u32 *pcap);
0291 int opal_set_powercap(u32 handle, int token, u32 pcap);
0292 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
0293 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
0294 int opal_sensor_group_clear(u32 group_hndl, int token);
0295 int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
0296 int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
0297
0298 int opal_secvar_get(const char *key, uint64_t key_len, u8 *data,
0299             uint64_t *data_size);
0300 int opal_secvar_get_next(const char *key, uint64_t *key_len,
0301              uint64_t key_buf_size);
0302 int opal_secvar_enqueue_update(const char *key, uint64_t key_len, u8 *data,
0303                    uint64_t data_size);
0304
0305 s64 opal_mpipl_update(enum opal_mpipl_ops op, u64 src, u64 dest, u64 size);
0306 s64 opal_mpipl_register_tag(enum opal_mpipl_tags tag, u64 addr);
0307 s64 opal_mpipl_query_tag(enum opal_mpipl_tags tag, __be64 *addr);
0308
0309 s64 opal_signal_system_reset(s32 cpu);
0310 s64 opal_quiesce(u64 shutdown_type, s32 cpu);
0311
0312 /* Internal functions */
0313 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
0314                    int depth, void *data);
0315 extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
0316                  const char *uname, int depth, void *data);
0317 void __init opal_configure_cores(void);
0318
0319 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
0320 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
0321 extern int opal_put_chars_atomic(uint32_t vtermno, const char *buf, int total_len);
0322 extern int opal_flush_chars(uint32_t vtermno, bool wait);
0323 extern int opal_flush_console(uint32_t vtermno);
0324
0325 extern void hvc_opal_init_early(void);
0326
0327 extern int opal_notifier_register(struct notifier_block *nb);
0328 extern int opal_notifier_unregister(struct notifier_block *nb);
0329
0330 extern int opal_message_notifier_register(enum opal_msg_type msg_type,
0331                         struct notifier_block *nb);
0332 extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
0333                         struct notifier_block *nb);
0334 extern void opal_notifier_enable(void);
0335 extern void opal_notifier_disable(void);
0336 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
0337
0338 extern int opal_async_get_token_interruptible(void);
0339 extern int opal_async_release_token(int token);
0340 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
0341 extern int opal_async_wait_response_interruptible(uint64_t token,
0342         struct opal_msg *msg);
0343 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
0344 extern int opal_get_sensor_data_u64(u32 sensor_hndl, u64 *sensor_data);
0345 extern int sensor_group_enable(u32 grp_hndl, bool enable);
0346
0347 struct rtc_time;
0348 extern time64_t opal_get_boot_time(void);
0349 extern void opal_nvram_init(void);
0350 extern void opal_flash_update_init(void);
0351 extern void opal_flash_update_print_message(void);
0352 extern int opal_elog_init(void);
0353 extern void opal_platform_dump_init(void);
0354 extern void opal_sys_param_init(void);
0355 extern void opal_msglog_init(void);
0356 extern void opal_msglog_sysfs_init(void);
0357 extern int opal_async_comp_init(void);
0358 extern int opal_sensor_init(void);
0359 extern int opal_hmi_handler_init(void);
0360 extern int opal_event_init(void);
0361 int opal_power_control_init(void);
0362
0363 extern int opal_machine_check(struct pt_regs *regs);
0364 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
0365 extern int opal_hmi_exception_early(struct pt_regs *regs);
0366 extern int opal_hmi_exception_early2(struct pt_regs *regs);
0367 extern int opal_handle_hmi_exception(struct pt_regs *regs);
0368
0369 extern void opal_shutdown(void);
0370 extern int opal_resync_timebase(void);
0371
0372 extern void opal_lpc_init(void);
0373
0374 extern void opal_kmsg_init(void);
0375
0376 extern int opal_event_request(unsigned int opal_event_nr);
0377
0378 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
0379                          unsigned long vmalloc_size);
0380 void opal_free_sg_list(struct opal_sg_list *sg);
0381
0382 extern int opal_error_code(int rc);
0383
0384 ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
0385
0386 static inline int opal_get_async_rc(struct opal_msg msg)
0387 {
0388     if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
0389         return OPAL_PARAMETER;
0390     else
0391         return be64_to_cpu(msg.params[1]);
0392 }
0393
0394 void opal_wake_poller(void);
0395
0396 void opal_powercap_init(void);
0397 void opal_psr_init(void);
0398 void opal_sensor_groups_init(void);
0399
0400 #endif /* __ASSEMBLY__ */
0401
0402 #endif /* _ASM_POWERPC_OPAL_H */