asm/nohash/pte-book3e.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
0003 #define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
0004 #ifdef __KERNEL__
0005
0006 /* PTE bit definitions for processors compliant to the Book3E
0007  * architecture 2.06 or later. The position of the PTE bits
0008  * matches the HW definition of the optional Embedded Page Table
0009  * category.
0010  */
0011
0012 /* Architected bits */
0013 #define _PAGE_PRESENT   0x000001 /* software: pte contains a translation */
0014 #define _PAGE_SW1   0x000002
0015 #define _PAGE_BIT_SWAP_TYPE 2
0016 #define _PAGE_BAP_SR    0x000004
0017 #define _PAGE_BAP_UR    0x000008
0018 #define _PAGE_BAP_SW    0x000010
0019 #define _PAGE_BAP_UW    0x000020
0020 #define _PAGE_BAP_SX    0x000040
0021 #define _PAGE_BAP_UX    0x000080
0022 #define _PAGE_PSIZE_MSK 0x000f00
0023 #define _PAGE_PSIZE_4K  0x000200
0024 #define _PAGE_PSIZE_8K  0x000300
0025 #define _PAGE_PSIZE_16K 0x000400
0026 #define _PAGE_PSIZE_32K 0x000500
0027 #define _PAGE_PSIZE_64K 0x000600
0028 #define _PAGE_PSIZE_128K    0x000700
0029 #define _PAGE_PSIZE_256K    0x000800
0030 #define _PAGE_PSIZE_512K    0x000900
0031 #define _PAGE_PSIZE_1M  0x000a00
0032 #define _PAGE_PSIZE_2M  0x000b00
0033 #define _PAGE_PSIZE_4M  0x000c00
0034 #define _PAGE_PSIZE_8M  0x000d00
0035 #define _PAGE_PSIZE_16M 0x000e00
0036 #define _PAGE_PSIZE_32M 0x000f00
0037 #define _PAGE_DIRTY 0x001000 /* C: page changed */
0038 #define _PAGE_SW0   0x002000
0039 #define _PAGE_U3    0x004000
0040 #define _PAGE_U2    0x008000
0041 #define _PAGE_U1    0x010000
0042 #define _PAGE_U0    0x020000
0043 #define _PAGE_ACCESSED  0x040000
0044 #define _PAGE_ENDIAN    0x080000
0045 #define _PAGE_GUARDED   0x100000
0046 #define _PAGE_COHERENT  0x200000 /* M: enforce memory coherence */
0047 #define _PAGE_NO_CACHE  0x400000 /* I: cache inhibit */
0048 #define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
0049
0050 /* "Higher level" linux bit combinations */
0051 #define _PAGE_EXEC      (_PAGE_BAP_SX | _PAGE_BAP_UX) /* .. and was cache cleaned */
0052 #define _PAGE_RW        (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
0053 #define _PAGE_KERNEL_RW     (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
0054 #define _PAGE_KERNEL_RO     (_PAGE_BAP_SR)
0055 #define _PAGE_KERNEL_RWX    (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
0056 #define _PAGE_KERNEL_ROX    (_PAGE_BAP_SR | _PAGE_BAP_SX)
0057 #define _PAGE_USER      (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
0058 #define _PAGE_PRIVILEGED    (_PAGE_BAP_SR)
0059
0060 #define _PAGE_SPECIAL   _PAGE_SW0
0061
0062 /* Base page size */
0063 #define _PAGE_PSIZE _PAGE_PSIZE_4K
0064 #define PTE_RPN_SHIFT   (24)
0065
0066 #define PTE_WIMGE_SHIFT (19)
0067 #define PTE_BAP_SHIFT   (2)
0068
0069 /* On 32-bit, we never clear the top part of the PTE */
0070 #ifdef CONFIG_PPC32
0071 #define _PTE_NONE_MASK  0xffffffff00000000ULL
0072 #define _PMD_PRESENT    0
0073 #define _PMD_PRESENT_MASK (PAGE_MASK)
0074 #define _PMD_BAD    (~PAGE_MASK)
0075 #define _PMD_USER   0
0076 #else
0077 #define _PTE_NONE_MASK  0
0078 #endif
0079
0080 /*
0081  * We define 2 sets of base prot bits, one for basic pages (ie,
0082  * cacheable kernel and user pages) and one for non cacheable
0083  * pages. We always set _PAGE_COHERENT when SMP is enabled or
0084  * the processor might need it for DMA coherency.
0085  */
0086 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
0087 #if defined(CONFIG_SMP)
0088 #define _PAGE_BASE  (_PAGE_BASE_NC | _PAGE_COHERENT)
0089 #else
0090 #define _PAGE_BASE  (_PAGE_BASE_NC)
0091 #endif
0092
0093 /* Permission masks used to generate the __P and __S table */
0094 #define PAGE_NONE   __pgprot(_PAGE_BASE)
0095 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
0096 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_BAP_UX)
0097 #define PAGE_COPY   __pgprot(_PAGE_BASE | _PAGE_USER)
0098 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_BAP_UX)
0099 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
0100 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_BAP_UX)
0101
0102 #ifndef __ASSEMBLY__
0103 static inline pte_t pte_mkprivileged(pte_t pte)
0104 {
0105     return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED);
0106 }
0107
0108 #define pte_mkprivileged pte_mkprivileged
0109
0110 static inline pte_t pte_mkuser(pte_t pte)
0111 {
0112     return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER);
0113 }
0114
0115 #define pte_mkuser pte_mkuser
0116
0117 static inline pte_t pte_mkexec(pte_t pte)
0118 {
0119     if (pte_val(pte) & _PAGE_BAP_UR)
0120         return __pte((pte_val(pte) & ~_PAGE_BAP_SX) | _PAGE_BAP_UX);
0121     else
0122         return __pte((pte_val(pte) & ~_PAGE_BAP_UX) | _PAGE_BAP_SX);
0123 }
0124 #define pte_mkexec pte_mkexec
0125
0126 #endif /* __ASSEMBLY__ */
0127
0128 #endif /* __KERNEL__ */
0129 #endif /*  _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */