asm/nohash/pgtable.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
0003 #define _ASM_POWERPC_NOHASH_PGTABLE_H
0004
0005 #if defined(CONFIG_PPC64)
0006 #include <asm/nohash/64/pgtable.h>
0007 #else
0008 #include <asm/nohash/32/pgtable.h>
0009 #endif
0010
0011 /* Permission masks used for kernel mappings */
0012 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
0013 #define PAGE_KERNEL_NC  __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
0014 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
0015                  _PAGE_NO_CACHE | _PAGE_GUARDED)
0016 #define PAGE_KERNEL_X   __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
0017 #define PAGE_KERNEL_RO  __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
0018 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
0019
0020 /*
0021  * Protection used for kernel text. We want the debuggers to be able to
0022  * set breakpoints anywhere, so don't write protect the kernel text
0023  * on platforms where such control is possible.
0024  */
0025 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
0026     defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
0027 #define PAGE_KERNEL_TEXT    PAGE_KERNEL_X
0028 #else
0029 #define PAGE_KERNEL_TEXT    PAGE_KERNEL_ROX
0030 #endif
0031
0032 /* Make modules code happy. We don't set RO yet */
0033 #define PAGE_KERNEL_EXEC    PAGE_KERNEL_X
0034
0035 /* Advertise special mapping type for AGP */
0036 #define PAGE_AGP        (PAGE_KERNEL_NC)
0037 #define HAVE_PAGE_AGP
0038
0039 #ifndef __ASSEMBLY__
0040
0041 /* Generic accessors to PTE bits */
0042 #ifndef pte_write
0043 static inline int pte_write(pte_t pte)
0044 {
0045     return pte_val(pte) & _PAGE_RW;
0046 }
0047 #endif
0048 static inline int pte_read(pte_t pte)       { return 1; }
0049 static inline int pte_dirty(pte_t pte)      { return pte_val(pte) & _PAGE_DIRTY; }
0050 static inline int pte_special(pte_t pte)    { return pte_val(pte) & _PAGE_SPECIAL; }
0051 static inline int pte_none(pte_t pte)       { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
0052 static inline bool pte_hashpte(pte_t pte)   { return false; }
0053 static inline bool pte_ci(pte_t pte)        { return pte_val(pte) & _PAGE_NO_CACHE; }
0054 static inline bool pte_exec(pte_t pte)      { return pte_val(pte) & _PAGE_EXEC; }
0055
0056 #ifdef CONFIG_NUMA_BALANCING
0057 /*
0058  * These work without NUMA balancing but the kernel does not care. See the
0059  * comment in include/linux/pgtable.h . On powerpc, this will only
0060  * work for user pages and always return true for kernel pages.
0061  */
0062 static inline int pte_protnone(pte_t pte)
0063 {
0064     return pte_present(pte) && !pte_user(pte);
0065 }
0066
0067 static inline int pmd_protnone(pmd_t pmd)
0068 {
0069     return pte_protnone(pmd_pte(pmd));
0070 }
0071 #endif /* CONFIG_NUMA_BALANCING */
0072
0073 static inline int pte_present(pte_t pte)
0074 {
0075     return pte_val(pte) & _PAGE_PRESENT;
0076 }
0077
0078 static inline bool pte_hw_valid(pte_t pte)
0079 {
0080     return pte_val(pte) & _PAGE_PRESENT;
0081 }
0082
0083 /*
0084  * Don't just check for any non zero bits in __PAGE_USER, since for book3e
0085  * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
0086  * _PAGE_USER.  Need to explicitly match _PAGE_BAP_UR bit in that case too.
0087  */
0088 #ifndef pte_user
0089 static inline bool pte_user(pte_t pte)
0090 {
0091     return (pte_val(pte) & _PAGE_USER) == _PAGE_USER;
0092 }
0093 #endif
0094
0095 /*
0096  * We only find page table entry in the last level
0097  * Hence no need for other accessors
0098  */
0099 #define pte_access_permitted pte_access_permitted
0100 static inline bool pte_access_permitted(pte_t pte, bool write)
0101 {
0102     /*
0103      * A read-only access is controlled by _PAGE_USER bit.
0104      * We have _PAGE_READ set for WRITE and EXECUTE
0105      */
0106     if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
0107         return false;
0108
0109     if (write && !pte_write(pte))
0110         return false;
0111
0112     return true;
0113 }
0114
0115 /* Conversion functions: convert a page and protection to a page entry,
0116  * and a page entry and page directory to the page they refer to.
0117  *
0118  * Even if PTEs can be unsigned long long, a PFN is always an unsigned
0119  * long for now.
0120  */
0121 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
0122     return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
0123              pgprot_val(pgprot)); }
0124 static inline unsigned long pte_pfn(pte_t pte)  {
0125     return pte_val(pte) >> PTE_RPN_SHIFT; }
0126
0127 /* Generic modifiers for PTE bits */
0128 static inline pte_t pte_exprotect(pte_t pte)
0129 {
0130     return __pte(pte_val(pte) & ~_PAGE_EXEC);
0131 }
0132
0133 static inline pte_t pte_mkclean(pte_t pte)
0134 {
0135     return __pte(pte_val(pte) & ~_PAGE_DIRTY);
0136 }
0137
0138 static inline pte_t pte_mkold(pte_t pte)
0139 {
0140     return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
0141 }
0142
0143 static inline pte_t pte_mkspecial(pte_t pte)
0144 {
0145     return __pte(pte_val(pte) | _PAGE_SPECIAL);
0146 }
0147
0148 #ifndef pte_mkhuge
0149 static inline pte_t pte_mkhuge(pte_t pte)
0150 {
0151     return __pte(pte_val(pte));
0152 }
0153 #endif
0154
0155 #ifndef pte_mkprivileged
0156 static inline pte_t pte_mkprivileged(pte_t pte)
0157 {
0158     return __pte(pte_val(pte) & ~_PAGE_USER);
0159 }
0160 #endif
0161
0162 #ifndef pte_mkuser
0163 static inline pte_t pte_mkuser(pte_t pte)
0164 {
0165     return __pte(pte_val(pte) | _PAGE_USER);
0166 }
0167 #endif
0168
0169 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
0170 {
0171     return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
0172 }
0173
0174 /* Insert a PTE, top-level function is out of line. It uses an inline
0175  * low level function in the respective pgtable-* files
0176  */
0177 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
0178                pte_t pte);
0179
0180 /* This low level function performs the actual PTE insertion
0181  * Setting the PTE depends on the MMU type and other factors. It's
0182  * an horrible mess that I'm not going to try to clean up now but
0183  * I'm keeping it in one place rather than spread around
0184  */
0185 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
0186                 pte_t *ptep, pte_t pte, int percpu)
0187 {
0188     /* Second case is 32-bit with 64-bit PTE.  In this case, we
0189      * can just store as long as we do the two halves in the right order
0190      * with a barrier in between.
0191      * In the percpu case, we also fallback to the simple update
0192      */
0193     if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) {
0194         __asm__ __volatile__("\
0195             stw%X0 %2,%0\n\
0196             mbar\n\
0197             stw%X1 %L2,%1"
0198         : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
0199         : "r" (pte) : "memory");
0200         return;
0201     }
0202     /* Anything else just stores the PTE normally. That covers all 64-bit
0203      * cases, and 32-bit non-hash with 32-bit PTEs.
0204      */
0205 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
0206     ptep->pte = ptep->pte1 = ptep->pte2 = ptep->pte3 = pte_val(pte);
0207 #else
0208     *ptep = pte;
0209 #endif
0210
0211     /*
0212      * With hardware tablewalk, a sync is needed to ensure that
0213      * subsequent accesses see the PTE we just wrote.  Unlike userspace
0214      * mappings, we can't tolerate spurious faults, so make sure
0215      * the new PTE will be seen the first time.
0216      */
0217     if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr))
0218         mb();
0219 }
0220
0221
0222 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
0223 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
0224                  pte_t *ptep, pte_t entry, int dirty);
0225
0226 /*
0227  * Macro to mark a page protection value as "uncacheable".
0228  */
0229
0230 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
0231              _PAGE_WRITETHRU)
0232
0233 #define pgprot_noncached(prot)    (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
0234                             _PAGE_NO_CACHE | _PAGE_GUARDED))
0235
0236 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
0237                             _PAGE_NO_CACHE))
0238
0239 #define pgprot_cached(prot)       (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
0240                             _PAGE_COHERENT))
0241
0242 #if _PAGE_WRITETHRU != 0
0243 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
0244                             _PAGE_COHERENT | _PAGE_WRITETHRU))
0245 #else
0246 #define pgprot_cached_wthru(prot)   pgprot_noncached(prot)
0247 #endif
0248
0249 #define pgprot_cached_noncoherent(prot) \
0250         (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
0251
0252 #define pgprot_writecombine pgprot_noncached_wc
0253
0254 struct file;
0255 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
0256                      unsigned long size, pgprot_t vma_prot);
0257 #define __HAVE_PHYS_MEM_ACCESS_PROT
0258
0259 #ifdef CONFIG_HUGETLB_PAGE
0260 static inline int hugepd_ok(hugepd_t hpd)
0261 {
0262 #ifdef CONFIG_PPC_8xx
0263     return ((hpd_val(hpd) & _PMD_PAGE_MASK) == _PMD_PAGE_8M);
0264 #else
0265     /* We clear the top bit to indicate hugepd */
0266     return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0);
0267 #endif
0268 }
0269
0270 static inline int pmd_huge(pmd_t pmd)
0271 {
0272     return 0;
0273 }
0274
0275 static inline int pud_huge(pud_t pud)
0276 {
0277     return 0;
0278 }
0279
0280 static inline int pgd_huge(pgd_t pgd)
0281 {
0282     return 0;
0283 }
0284 #define pgd_huge        pgd_huge
0285
0286 #define is_hugepd(hpd)      (hugepd_ok(hpd))
0287 #endif
0288
0289 /*
0290  * This gets called at the end of handling a page fault, when
0291  * the kernel has put a new PTE into the page table for the process.
0292  * We use it to ensure coherency between the i-cache and d-cache
0293  * for the page which has just been mapped in.
0294  */
0295 #if defined(CONFIG_PPC_FSL_BOOK3E) && defined(CONFIG_HUGETLB_PAGE)
0296 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep);
0297 #else
0298 static inline
0299 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) {}
0300 #endif
0301
0302 #endif /* __ASSEMBLY__ */
0303 #endif