nohash/32/pte-fsl-booke.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
0003 #define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
0004 #ifdef __KERNEL__
0005
0006 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
0007  * processors
0008  *
0009    MMU Assist Register 3:
0010
0011    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
0012    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
0013
0014    - PRESENT *must* be in the bottom three bits because swap cache
0015      entries use the top 29 bits.
0016
0017 */
0018
0019 /* Definitions for FSL Book-E Cores */
0020 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
0021 #define _PAGE_USER  0x00002 /* S: User page (maps to UR) */
0022 #define _PAGE_RW    0x00004 /* S: Write permission (SW) */
0023 #define _PAGE_DIRTY 0x00008 /* S: Page dirty */
0024 #define _PAGE_EXEC  0x00010 /* H: SX permission */
0025 #define _PAGE_ACCESSED  0x00020 /* S: Page referenced */
0026
0027 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
0028 #define _PAGE_GUARDED   0x00080 /* H: G bit */
0029 #define _PAGE_COHERENT  0x00100 /* H: M bit */
0030 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
0031 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
0032 #define _PAGE_SPECIAL   0x00800 /* S: Special page */
0033
0034 #define _PAGE_KERNEL_RO     0
0035 #define _PAGE_KERNEL_ROX    _PAGE_EXEC
0036 #define _PAGE_KERNEL_RW     (_PAGE_DIRTY | _PAGE_RW)
0037 #define _PAGE_KERNEL_RWX    (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
0038
0039 /* No page size encoding in the linux PTE */
0040 #define _PAGE_PSIZE     0
0041
0042 #define _PMD_PRESENT    0
0043 #define _PMD_PRESENT_MASK (PAGE_MASK)
0044 #define _PMD_BAD    (~PAGE_MASK)
0045 #define _PMD_USER   0
0046
0047 #define _PTE_NONE_MASK  0
0048
0049 #define PTE_WIMGE_SHIFT (6)
0050
0051 /*
0052  * We define 2 sets of base prot bits, one for basic pages (ie,
0053  * cacheable kernel and user pages) and one for non cacheable
0054  * pages. We always set _PAGE_COHERENT when SMP is enabled or
0055  * the processor might need it for DMA coherency.
0056  */
0057 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED)
0058 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
0059 #define _PAGE_BASE  (_PAGE_BASE_NC | _PAGE_COHERENT)
0060 #else
0061 #define _PAGE_BASE  (_PAGE_BASE_NC)
0062 #endif
0063
0064 /* Permission masks used to generate the __P and __S table */
0065 #define PAGE_NONE   __pgprot(_PAGE_BASE)
0066 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
0067 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
0068 #define PAGE_COPY   __pgprot(_PAGE_BASE | _PAGE_USER)
0069 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
0070 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
0071 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
0072
0073 #endif /* __KERNEL__ */
0074 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */