nohash/32/pte-8xx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
0003 #define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
0004 #ifdef __KERNEL__
0005
0006 /*
0007  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
0008  * We also use the two level tables, but we can put the real bits in them
0009  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
0010  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
0011  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
0012  * based upon user/super access.  The TLB does not have accessed nor write
0013  * protect.  We assume that if the TLB get loaded with an entry it is
0014  * accessed, and overload the changed bit for write protect.  We use
0015  * two bits in the software pte that are supposed to be set to zero in
0016  * the TLB entry (24 and 25) for these indicators.  Although the level 1
0017  * descriptor contains the guarded and writethrough/copyback bits, we can
0018  * set these at the page level since they get copied from the Mx_TWC
0019  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
0020  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
0021  * These will get masked from the level 2 descriptor at TLB load time, and
0022  * copied to the MD_TWC before it gets loaded.
0023  * Large page sizes added.  We currently support two sizes, 4K and 8M.
0024  * This also allows a TLB hander optimization because we can directly
0025  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
0026  * mapping of well known areas.  The PMD (PGD) entries contain control
0027  * flags in addition to the address, so care must be taken that the
0028  * software no longer assumes these are only pointers.
0029  */
0030
0031 /* Definitions for 8xx embedded chips. */
0032 #define _PAGE_PRESENT   0x0001  /* V: Page is valid */
0033 #define _PAGE_NO_CACHE  0x0002  /* CI: cache inhibit */
0034 #define _PAGE_SH    0x0004  /* SH: No ASID (context) compare */
0035 #define _PAGE_SPS   0x0008  /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
0036 #define _PAGE_DIRTY 0x0100  /* C: page changed */
0037
0038 /* These 4 software bits must be masked out when the L2 entry is loaded
0039  * into the TLB.
0040  */
0041 #define _PAGE_GUARDED   0x0010  /* Copied to L1 G entry in DTLB */
0042 #define _PAGE_ACCESSED  0x0020  /* Copied to L1 APG 1 entry in I/DTLB */
0043 #define _PAGE_EXEC  0x0040  /* Copied to PP (bit 21) in ITLB */
0044 #define _PAGE_SPECIAL   0x0080  /* SW entry */
0045
0046 #define _PAGE_NA    0x0200  /* Supervisor NA, User no access */
0047 #define _PAGE_RO    0x0600  /* Supervisor RO, User no access */
0048
0049 #define _PAGE_HUGE  0x0800  /* Copied to L1 PS bit 29 */
0050
0051 /* cache related flags non existing on 8xx */
0052 #define _PAGE_COHERENT  0
0053 #define _PAGE_WRITETHRU 0
0054
0055 #define _PAGE_KERNEL_RO     (_PAGE_SH | _PAGE_RO)
0056 #define _PAGE_KERNEL_ROX    (_PAGE_SH | _PAGE_RO | _PAGE_EXEC)
0057 #define _PAGE_KERNEL_RW     (_PAGE_SH | _PAGE_DIRTY)
0058 #define _PAGE_KERNEL_RWX    (_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
0059
0060 #define _PMD_PRESENT    0x0001
0061 #define _PMD_PRESENT_MASK   _PMD_PRESENT
0062 #define _PMD_BAD    0x0f90
0063 #define _PMD_PAGE_MASK  0x000c
0064 #define _PMD_PAGE_8M    0x000c
0065 #define _PMD_PAGE_512K  0x0004
0066 #define _PMD_ACCESSED   0x0020  /* APG 1 */
0067 #define _PMD_USER   0x0040  /* APG 2 */
0068
0069 #define _PTE_NONE_MASK  0
0070
0071 #ifdef CONFIG_PPC_16K_PAGES
0072 #define _PAGE_PSIZE _PAGE_SPS
0073 #else
0074 #define _PAGE_PSIZE     0
0075 #endif
0076
0077 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
0078 #define _PAGE_BASE  (_PAGE_BASE_NC)
0079
0080 /* Permission masks used to generate the __P and __S table */
0081 #define PAGE_NONE   __pgprot(_PAGE_BASE | _PAGE_NA)
0082 #define PAGE_SHARED __pgprot(_PAGE_BASE)
0083 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_EXEC)
0084 #define PAGE_COPY   __pgprot(_PAGE_BASE | _PAGE_RO)
0085 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
0086 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_RO)
0087 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
0088
0089 #ifndef __ASSEMBLY__
0090 static inline pte_t pte_wrprotect(pte_t pte)
0091 {
0092     return __pte(pte_val(pte) | _PAGE_RO);
0093 }
0094
0095 #define pte_wrprotect pte_wrprotect
0096
0097 static inline int pte_write(pte_t pte)
0098 {
0099     return !(pte_val(pte) & _PAGE_RO);
0100 }
0101
0102 #define pte_write pte_write
0103
0104 static inline pte_t pte_mkwrite(pte_t pte)
0105 {
0106     return __pte(pte_val(pte) & ~_PAGE_RO);
0107 }
0108
0109 #define pte_mkwrite pte_mkwrite
0110
0111 static inline bool pte_user(pte_t pte)
0112 {
0113     return !(pte_val(pte) & _PAGE_SH);
0114 }
0115
0116 #define pte_user pte_user
0117
0118 static inline pte_t pte_mkprivileged(pte_t pte)
0119 {
0120     return __pte(pte_val(pte) | _PAGE_SH);
0121 }
0122
0123 #define pte_mkprivileged pte_mkprivileged
0124
0125 static inline pte_t pte_mkuser(pte_t pte)
0126 {
0127     return __pte(pte_val(pte) & ~_PAGE_SH);
0128 }
0129
0130 #define pte_mkuser pte_mkuser
0131
0132 static inline pte_t pte_mkhuge(pte_t pte)
0133 {
0134     return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE);
0135 }
0136
0137 #define pte_mkhuge pte_mkhuge
0138
0139 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
0140                      unsigned long clr, unsigned long set, int huge);
0141
0142 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
0143 {
0144     pte_update(mm, addr, ptep, 0, _PAGE_RO, 0);
0145 }
0146 #define ptep_set_wrprotect ptep_set_wrprotect
0147
0148 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
0149                        pte_t entry, unsigned long address, int psize)
0150 {
0151     unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_EXEC);
0152     unsigned long clr = ~pte_val(entry) & _PAGE_RO;
0153     int huge = psize > mmu_virtual_psize ? 1 : 0;
0154
0155     pte_update(vma->vm_mm, address, ptep, clr, set, huge);
0156
0157     flush_tlb_page(vma, address);
0158 }
0159 #define __ptep_set_access_flags __ptep_set_access_flags
0160
0161 static inline unsigned long pgd_leaf_size(pgd_t pgd)
0162 {
0163     if (pgd_val(pgd) & _PMD_PAGE_8M)
0164         return SZ_8M;
0165     return SZ_4M;
0166 }
0167
0168 #define pgd_leaf_size pgd_leaf_size
0169
0170 static inline unsigned long pte_leaf_size(pte_t pte)
0171 {
0172     pte_basic_t val = pte_val(pte);
0173
0174     if (val & _PAGE_HUGE)
0175         return SZ_512K;
0176     if (val & _PAGE_SPS)
0177         return SZ_16K;
0178     return SZ_4K;
0179 }
0180
0181 #define pte_leaf_size pte_leaf_size
0182
0183 #endif
0184
0185 #endif /* __KERNEL__ */
0186 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_8xx_H */