nohash/32/pte-40x.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_32_PTE_40x_H
0003 #define _ASM_POWERPC_NOHASH_32_PTE_40x_H
0004 #ifdef __KERNEL__
0005
0006 /*
0007  * At present, all PowerPC 400-class processors share a similar TLB
0008  * architecture. The instruction and data sides share a unified,
0009  * 64-entry, fully-associative TLB which is maintained totally under
0010  * software control. In addition, the instruction side has a
0011  * hardware-managed, 4-entry, fully-associative TLB which serves as a
0012  * first level to the shared TLB. These two TLBs are known as the UTLB
0013  * and ITLB, respectively (see "mmu.h" for definitions).
0014  *
0015  * There are several potential gotchas here.  The 40x hardware TLBLO
0016  * field looks like this:
0017  *
0018  * 0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0019  * RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
0020  *
0021  * Where possible we make the Linux PTE bits match up with this
0022  *
0023  * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
0024  *   support down to 1k pages), this is done in the TLBMiss exception
0025  *   handler.
0026  * - We use only zones 0 (for kernel pages) and 1 (for user pages)
0027  *   of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
0028  *   miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
0029  *   zone.
0030  * - PRESENT *must* be in the bottom two bits because swap cache
0031  *   entries use the top 30 bits.  Because 40x doesn't support SMP
0032  *   anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
0033  *   is cleared in the TLB miss handler before the TLB entry is loaded.
0034  * - All other bits of the PTE are loaded into TLBLO without
0035  *   modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
0036  *   software PTE bits.  We actually use bits 21, 24, 25, and
0037  *   30 respectively for the software bits: ACCESSED, DIRTY, RW, and
0038  *   PRESENT.
0039  */
0040
0041 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
0042 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
0043 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
0044 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
0045 #define _PAGE_USER  0x010   /* matches one of the zone permission bits */
0046 #define _PAGE_SPECIAL   0x020   /* software: Special page */
0047 #define _PAGE_DIRTY 0x080   /* software: dirty page */
0048 #define _PAGE_RW    0x100   /* hardware: WR, anded with dirty in exception */
0049 #define _PAGE_EXEC  0x200   /* hardware: EX permission */
0050 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
0051
0052 /* No page size encoding in the linux PTE */
0053 #define _PAGE_PSIZE     0
0054
0055 /* cache related flags non existing on 40x */
0056 #define _PAGE_COHERENT  0
0057
0058 #define _PAGE_KERNEL_RO     0
0059 #define _PAGE_KERNEL_ROX    _PAGE_EXEC
0060 #define _PAGE_KERNEL_RW     (_PAGE_DIRTY | _PAGE_RW)
0061 #define _PAGE_KERNEL_RWX    (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
0062
0063 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
0064 #define _PMD_PRESENT_MASK   _PMD_PRESENT
0065 #define _PMD_BAD    0x802
0066 #define _PMD_SIZE_4M    0x0c0
0067 #define _PMD_SIZE_16M   0x0e0
0068 #define _PMD_USER   0
0069
0070 #define _PTE_NONE_MASK  0
0071
0072 /* Until my rework is finished, 40x still needs atomic PTE updates */
0073 #define PTE_ATOMIC_UPDATES  1
0074
0075 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED)
0076 #define _PAGE_BASE  (_PAGE_BASE_NC)
0077
0078 /* Permission masks used to generate the __P and __S table */
0079 #define PAGE_NONE   __pgprot(_PAGE_BASE)
0080 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
0081 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
0082 #define PAGE_COPY   __pgprot(_PAGE_BASE | _PAGE_USER)
0083 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
0084 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
0085 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
0086
0087 #endif /* __KERNEL__ */
0088 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_40x_H */