nohash/32/pgtable.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
0003 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H
0004
0005 #include <asm-generic/pgtable-nopmd.h>
0006
0007 #ifndef __ASSEMBLY__
0008 #include <linux/sched.h>
0009 #include <linux/threads.h>
0010 #include <asm/mmu.h>            /* For sub-arch specific PPC_PIN_SIZE */
0011
0012 #ifdef CONFIG_44x
0013 extern int icache_44x_need_flush;
0014 #endif
0015
0016 #endif /* __ASSEMBLY__ */
0017
0018 #define PTE_INDEX_SIZE  PTE_SHIFT
0019 #define PMD_INDEX_SIZE  0
0020 #define PUD_INDEX_SIZE  0
0021 #define PGD_INDEX_SIZE  (32 - PGDIR_SHIFT)
0022
0023 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
0024 #define PUD_CACHE_INDEX PUD_INDEX_SIZE
0025
0026 #ifndef __ASSEMBLY__
0027 #define PTE_TABLE_SIZE  (sizeof(pte_t) << PTE_INDEX_SIZE)
0028 #define PMD_TABLE_SIZE  0
0029 #define PUD_TABLE_SIZE  0
0030 #define PGD_TABLE_SIZE  (sizeof(pgd_t) << PGD_INDEX_SIZE)
0031
0032 #define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1)
0033 #endif  /* __ASSEMBLY__ */
0034
0035 #define PTRS_PER_PTE    (1 << PTE_INDEX_SIZE)
0036 #define PTRS_PER_PGD    (1 << PGD_INDEX_SIZE)
0037
0038 /*
0039  * The normal case is that PTEs are 32-bits and we have a 1-page
0040  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
0041  *
0042  * For any >32-bit physical address platform, we can use the following
0043  * two level page table layout where the pgdir is 8KB and the MS 13 bits
0044  * are an index to the second level table.  The combined pgdir/pmd first
0045  * level has 2048 entries and the second level has 512 64-bit PTE entries.
0046  * -Matt
0047  */
0048 /* PGDIR_SHIFT determines what a top-level page table entry can map */
0049 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
0050 #define PGDIR_SIZE  (1UL << PGDIR_SHIFT)
0051 #define PGDIR_MASK  (~(PGDIR_SIZE-1))
0052
0053 /* Bits to mask out from a PGD to get to the PUD page */
0054 #define PGD_MASKED_BITS     0
0055
0056 #define USER_PTRS_PER_PGD   (TASK_SIZE / PGDIR_SIZE)
0057
0058 #define pte_ERROR(e) \
0059     pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
0060         (unsigned long long)pte_val(e))
0061 #define pgd_ERROR(e) \
0062     pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
0063
0064 #ifndef __ASSEMBLY__
0065
0066 int map_kernel_page(unsigned long va, phys_addr_t pa, pgprot_t prot);
0067 void unmap_kernel_page(unsigned long va);
0068
0069 #endif /* !__ASSEMBLY__ */
0070
0071
0072 /*
0073  * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
0074  * value (for now) on others, from where we can start layout kernel
0075  * virtual space that goes below PKMAP and FIXMAP
0076  */
0077 #include <asm/fixmap.h>
0078
0079 /*
0080  * ioremap_bot starts at that address. Early ioremaps move down from there,
0081  * until mem_init() at which point this becomes the top of the vmalloc
0082  * and ioremap space
0083  */
0084 #ifdef CONFIG_HIGHMEM
0085 #define IOREMAP_TOP PKMAP_BASE
0086 #else
0087 #define IOREMAP_TOP FIXADDR_START
0088 #endif
0089
0090 /* PPC32 shares vmalloc area with ioremap */
0091 #define IOREMAP_START   VMALLOC_START
0092 #define IOREMAP_END VMALLOC_END
0093
0094 /*
0095  * Just any arbitrary offset to the start of the vmalloc VM area: the
0096  * current 16MB value just means that there will be a 64MB "hole" after the
0097  * physical memory until the kernel virtual memory starts.  That means that
0098  * any out-of-bounds memory accesses will hopefully be caught.
0099  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
0100  * area for the same reason. ;)
0101  *
0102  * We no longer map larger than phys RAM with the BATs so we don't have
0103  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
0104  * about clashes between our early calls to ioremap() that start growing down
0105  * from IOREMAP_TOP being run into the VM area allocations (growing upwards
0106  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
0107  * we actually run into our mappings setup in the early boot with the VM
0108  * system.  This really does become a problem for machines with good amounts
0109  * of RAM.  -- Cort
0110  */
0111 #define VMALLOC_OFFSET (0x1000000) /* 16M */
0112 #ifdef PPC_PIN_SIZE
0113 #define VMALLOC_START (((ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
0114 #else
0115 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
0116 #endif
0117
0118 #ifdef CONFIG_KASAN_VMALLOC
0119 #define VMALLOC_END ALIGN_DOWN(ioremap_bot, PAGE_SIZE << KASAN_SHADOW_SCALE_SHIFT)
0120 #else
0121 #define VMALLOC_END ioremap_bot
0122 #endif
0123
0124 /*
0125  * Bits in a linux-style PTE.  These match the bits in the
0126  * (hardware-defined) PowerPC PTE as closely as possible.
0127  */
0128
0129 #if defined(CONFIG_40x)
0130 #include <asm/nohash/32/pte-40x.h>
0131 #elif defined(CONFIG_44x)
0132 #include <asm/nohash/32/pte-44x.h>
0133 #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
0134 #include <asm/nohash/pte-book3e.h>
0135 #elif defined(CONFIG_FSL_BOOKE)
0136 #include <asm/nohash/32/pte-fsl-booke.h>
0137 #elif defined(CONFIG_PPC_8xx)
0138 #include <asm/nohash/32/pte-8xx.h>
0139 #endif
0140
0141 /*
0142  * Location of the PFN in the PTE. Most 32-bit platforms use the same
0143  * as _PAGE_SHIFT here (ie, naturally aligned).
0144  * Platform who don't just pre-define the value so we don't override it here.
0145  */
0146 #ifndef PTE_RPN_SHIFT
0147 #define PTE_RPN_SHIFT   (PAGE_SHIFT)
0148 #endif
0149
0150 /*
0151  * The mask covered by the RPN must be a ULL on 32-bit platforms with
0152  * 64-bit PTEs.
0153  */
0154 #if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
0155 #define PTE_RPN_MASK    (~((1ULL << PTE_RPN_SHIFT) - 1))
0156 #define MAX_POSSIBLE_PHYSMEM_BITS 36
0157 #else
0158 #define PTE_RPN_MASK    (~((1UL << PTE_RPN_SHIFT) - 1))
0159 #define MAX_POSSIBLE_PHYSMEM_BITS 32
0160 #endif
0161
0162 /*
0163  * _PAGE_CHG_MASK masks of bits that are to be preserved across
0164  * pgprot changes.
0165  */
0166 #define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPECIAL)
0167
0168 #ifndef __ASSEMBLY__
0169
0170 #define pte_clear(mm, addr, ptep) \
0171     do { pte_update(mm, addr, ptep, ~0, 0, 0); } while (0)
0172
0173 #ifndef pte_mkwrite
0174 static inline pte_t pte_mkwrite(pte_t pte)
0175 {
0176     return __pte(pte_val(pte) | _PAGE_RW);
0177 }
0178 #endif
0179
0180 static inline pte_t pte_mkdirty(pte_t pte)
0181 {
0182     return __pte(pte_val(pte) | _PAGE_DIRTY);
0183 }
0184
0185 static inline pte_t pte_mkyoung(pte_t pte)
0186 {
0187     return __pte(pte_val(pte) | _PAGE_ACCESSED);
0188 }
0189
0190 #ifndef pte_wrprotect
0191 static inline pte_t pte_wrprotect(pte_t pte)
0192 {
0193     return __pte(pte_val(pte) & ~_PAGE_RW);
0194 }
0195 #endif
0196
0197 #ifndef pte_mkexec
0198 static inline pte_t pte_mkexec(pte_t pte)
0199 {
0200     return __pte(pte_val(pte) | _PAGE_EXEC);
0201 }
0202 #endif
0203
0204 #define pmd_none(pmd)       (!pmd_val(pmd))
0205 #define pmd_bad(pmd)        (pmd_val(pmd) & _PMD_BAD)
0206 #define pmd_present(pmd)    (pmd_val(pmd) & _PMD_PRESENT_MASK)
0207 static inline void pmd_clear(pmd_t *pmdp)
0208 {
0209     *pmdp = __pmd(0);
0210 }
0211
0212 /*
0213  * PTE updates. This function is called whenever an existing
0214  * valid PTE is updated. This does -not- include set_pte_at()
0215  * which nowadays only sets a new PTE.
0216  *
0217  * Depending on the type of MMU, we may need to use atomic updates
0218  * and the PTE may be either 32 or 64 bit wide. In the later case,
0219  * when using atomic updates, only the low part of the PTE is
0220  * accessed atomically.
0221  *
0222  * In addition, on 44x, we also maintain a global flag indicating
0223  * that an executable user mapping was modified, which is needed
0224  * to properly flush the virtually tagged instruction cache of
0225  * those implementations.
0226  *
0227  * On the 8xx, the page tables are a bit special. For 16k pages, we have
0228  * 4 identical entries. For 512k pages, we have 128 entries as if it was
0229  * 4k pages, but they are flagged as 512k pages for the hardware.
0230  * For other page sizes, we have a single entry in the table.
0231  */
0232 #ifdef CONFIG_PPC_8xx
0233 static pmd_t *pmd_off(struct mm_struct *mm, unsigned long addr);
0234 static int hugepd_ok(hugepd_t hpd);
0235
0236 static int number_of_cells_per_pte(pmd_t *pmd, pte_basic_t val, int huge)
0237 {
0238     if (!huge)
0239         return PAGE_SIZE / SZ_4K;
0240     else if (hugepd_ok(*((hugepd_t *)pmd)))
0241         return 1;
0242     else if (IS_ENABLED(CONFIG_PPC_4K_PAGES) && !(val & _PAGE_HUGE))
0243         return SZ_16K / SZ_4K;
0244     else
0245         return SZ_512K / SZ_4K;
0246 }
0247
0248 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
0249                      unsigned long clr, unsigned long set, int huge)
0250 {
0251     pte_basic_t *entry = (pte_basic_t *)p;
0252     pte_basic_t old = pte_val(*p);
0253     pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
0254     int num, i;
0255     pmd_t *pmd = pmd_off(mm, addr);
0256
0257     num = number_of_cells_per_pte(pmd, new, huge);
0258
0259     for (i = 0; i < num; i++, entry++, new += SZ_4K)
0260         *entry = new;
0261
0262     return old;
0263 }
0264
0265 #ifdef CONFIG_PPC_16K_PAGES
0266 #define __HAVE_ARCH_PTEP_GET
0267 static inline pte_t ptep_get(pte_t *ptep)
0268 {
0269     pte_basic_t val = READ_ONCE(ptep->pte);
0270     pte_t pte = {val, val, val, val};
0271
0272     return pte;
0273 }
0274 #endif /* CONFIG_PPC_16K_PAGES */
0275
0276 #else
0277 static inline pte_basic_t pte_update(struct mm_struct *mm, unsigned long addr, pte_t *p,
0278                      unsigned long clr, unsigned long set, int huge)
0279 {
0280     pte_basic_t old = pte_val(*p);
0281     pte_basic_t new = (old & ~(pte_basic_t)clr) | set;
0282
0283     *p = __pte(new);
0284
0285 #ifdef CONFIG_44x
0286     if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
0287         icache_44x_need_flush = 1;
0288 #endif
0289     return old;
0290 }
0291 #endif
0292
0293 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
0294 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
0295                           unsigned long addr, pte_t *ptep)
0296 {
0297     unsigned long old;
0298     old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
0299     return (old & _PAGE_ACCESSED) != 0;
0300 }
0301 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
0302     __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep)
0303
0304 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
0305 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
0306                        pte_t *ptep)
0307 {
0308     return __pte(pte_update(mm, addr, ptep, ~0, 0, 0));
0309 }
0310
0311 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
0312 #ifndef ptep_set_wrprotect
0313 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
0314                       pte_t *ptep)
0315 {
0316     pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
0317 }
0318 #endif
0319
0320 #ifndef __ptep_set_access_flags
0321 static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
0322                        pte_t *ptep, pte_t entry,
0323                        unsigned long address,
0324                        int psize)
0325 {
0326     unsigned long set = pte_val(entry) &
0327                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
0328     int huge = psize > mmu_virtual_psize ? 1 : 0;
0329
0330     pte_update(vma->vm_mm, address, ptep, 0, set, huge);
0331
0332     flush_tlb_page(vma, address);
0333 }
0334 #endif
0335
0336 static inline int pte_young(pte_t pte)
0337 {
0338     return pte_val(pte) & _PAGE_ACCESSED;
0339 }
0340
0341 /*
0342  * Note that on Book E processors, the pmd contains the kernel virtual
0343  * (lowmem) address of the pte page.  The physical address is less useful
0344  * because everything runs with translation enabled (even the TLB miss
0345  * handler).  On everything else the pmd contains the physical address
0346  * of the pte page.  -- paulus
0347  */
0348 #ifndef CONFIG_BOOKE
0349 #define pmd_pfn(pmd)        (pmd_val(pmd) >> PAGE_SHIFT)
0350 #else
0351 #define pmd_page_vaddr(pmd) \
0352     ((unsigned long)(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
0353 #define pmd_pfn(pmd)        (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
0354 #endif
0355
0356 #define pmd_page(pmd)       pfn_to_page(pmd_pfn(pmd))
0357 /*
0358  * Encode and decode a swap entry.
0359  * Note that the bits we use in a PTE for representing a swap entry
0360  * must not include the _PAGE_PRESENT bit.
0361  *   -- paulus
0362  */
0363 #define __swp_type(entry)       ((entry).val & 0x1f)
0364 #define __swp_offset(entry)     ((entry).val >> 5)
0365 #define __swp_entry(type, offset)   ((swp_entry_t) { (type) | ((offset) << 5) })
0366 #define __pte_to_swp_entry(pte)     ((swp_entry_t) { pte_val(pte) >> 3 })
0367 #define __swp_entry_to_pte(x)       ((pte_t) { (x).val << 3 })
0368
0369 #endif /* !__ASSEMBLY__ */
0370
0371 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */