nohash/32/mmu-44x.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_MMU_44X_H_
0003 #define _ASM_POWERPC_MMU_44X_H_
0004 /*
0005  * PPC440 support
0006  */
0007
0008 #include <asm/asm-const.h>
0009
0010 #define PPC44x_MMUCR_TID    0x000000ff
0011 #define PPC44x_MMUCR_STS    0x00010000
0012
0013 #define PPC44x_TLB_PAGEID   0
0014 #define PPC44x_TLB_XLAT     1
0015 #define PPC44x_TLB_ATTRIB   2
0016
0017 /* Page identification fields */
0018 #define PPC44x_TLB_EPN_MASK 0xfffffc00      /* Effective Page Number */
0019 #define PPC44x_TLB_VALID    0x00000200      /* Valid flag */
0020 #define PPC44x_TLB_TS       0x00000100  /* Translation address space */
0021 #define PPC44x_TLB_1K       0x00000000  /* Page sizes */
0022 #define PPC44x_TLB_4K       0x00000010
0023 #define PPC44x_TLB_16K      0x00000020
0024 #define PPC44x_TLB_64K      0x00000030
0025 #define PPC44x_TLB_256K     0x00000040
0026 #define PPC44x_TLB_1M       0x00000050
0027 #define PPC44x_TLB_16M      0x00000070
0028 #define PPC44x_TLB_256M     0x00000090
0029
0030 /* Translation fields */
0031 #define PPC44x_TLB_RPN_MASK 0xfffffc00      /* Real Page Number */
0032 #define PPC44x_TLB_ERPN_MASK    0x0000000f
0033
0034 /* Storage attribute and access control fields */
0035 #define PPC44x_TLB_ATTR_MASK    0x0000ff80
0036 #define PPC44x_TLB_U0       0x00008000      /* User 0 */
0037 #define PPC44x_TLB_U1       0x00004000      /* User 1 */
0038 #define PPC44x_TLB_U2       0x00002000      /* User 2 */
0039 #define PPC44x_TLB_U3       0x00001000      /* User 3 */
0040 #define PPC44x_TLB_W        0x00000800      /* Caching is write-through */
0041 #define PPC44x_TLB_I        0x00000400      /* Caching is inhibited */
0042 #define PPC44x_TLB_M        0x00000200      /* Memory is coherent */
0043 #define PPC44x_TLB_G        0x00000100      /* Memory is guarded */
0044 #define PPC44x_TLB_E        0x00000080      /* Memory is little endian */
0045
0046 #define PPC44x_TLB_PERM_MASK    0x0000003f
0047 #define PPC44x_TLB_UX       0x00000020      /* User execution */
0048 #define PPC44x_TLB_UW       0x00000010      /* User write */
0049 #define PPC44x_TLB_UR       0x00000008      /* User read */
0050 #define PPC44x_TLB_SX       0x00000004      /* Super execution */
0051 #define PPC44x_TLB_SW       0x00000002      /* Super write */
0052 #define PPC44x_TLB_SR       0x00000001      /* Super read */
0053
0054 /* Number of TLB entries */
0055 #define PPC44x_TLB_SIZE     64
0056
0057 /* 47x bits */
0058 #define PPC47x_MMUCR_TID    0x0000ffff
0059 #define PPC47x_MMUCR_STS    0x00010000
0060
0061 /* Page identification fields */
0062 #define PPC47x_TLB0_EPN_MASK    0xfffff000      /* Effective Page Number */
0063 #define PPC47x_TLB0_VALID   0x00000800      /* Valid flag */
0064 #define PPC47x_TLB0_TS      0x00000400  /* Translation address space */
0065 #define PPC47x_TLB0_4K      0x00000000
0066 #define PPC47x_TLB0_16K     0x00000010
0067 #define PPC47x_TLB0_64K     0x00000030
0068 #define PPC47x_TLB0_1M      0x00000070
0069 #define PPC47x_TLB0_16M     0x000000f0
0070 #define PPC47x_TLB0_256M    0x000001f0
0071 #define PPC47x_TLB0_1G      0x000003f0
0072 #define PPC47x_TLB0_BOLTED_R    0x00000008  /* tlbre only */
0073
0074 /* Translation fields */
0075 #define PPC47x_TLB1_RPN_MASK    0xfffff000      /* Real Page Number */
0076 #define PPC47x_TLB1_ERPN_MASK   0x000003ff
0077
0078 /* Storage attribute and access control fields */
0079 #define PPC47x_TLB2_ATTR_MASK   0x0003ff80
0080 #define PPC47x_TLB2_IL1I    0x00020000      /* Memory is guarded */
0081 #define PPC47x_TLB2_IL1D    0x00010000      /* Memory is guarded */
0082 #define PPC47x_TLB2_U0      0x00008000      /* User 0 */
0083 #define PPC47x_TLB2_U1      0x00004000      /* User 1 */
0084 #define PPC47x_TLB2_U2      0x00002000      /* User 2 */
0085 #define PPC47x_TLB2_U3      0x00001000      /* User 3 */
0086 #define PPC47x_TLB2_W       0x00000800      /* Caching is write-through */
0087 #define PPC47x_TLB2_I       0x00000400      /* Caching is inhibited */
0088 #define PPC47x_TLB2_M       0x00000200      /* Memory is coherent */
0089 #define PPC47x_TLB2_G       0x00000100      /* Memory is guarded */
0090 #define PPC47x_TLB2_E       0x00000080      /* Memory is little endian */
0091 #define PPC47x_TLB2_PERM_MASK   0x0000003f
0092 #define PPC47x_TLB2_UX      0x00000020      /* User execution */
0093 #define PPC47x_TLB2_UW      0x00000010      /* User write */
0094 #define PPC47x_TLB2_UR      0x00000008      /* User read */
0095 #define PPC47x_TLB2_SX      0x00000004      /* Super execution */
0096 #define PPC47x_TLB2_SW      0x00000002      /* Super write */
0097 #define PPC47x_TLB2_SR      0x00000001      /* Super read */
0098 #define PPC47x_TLB2_U_RWX   (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR)
0099 #define PPC47x_TLB2_S_RWX   (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR)
0100 #define PPC47x_TLB2_S_RW    (PPC47x_TLB2_SW | PPC47x_TLB2_SR)
0101 #define PPC47x_TLB2_IMG     (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G)
0102
0103 #ifndef __ASSEMBLY__
0104
0105 extern unsigned int tlb_44x_hwater;
0106 extern unsigned int tlb_44x_index;
0107
0108 typedef struct {
0109     unsigned int    id;
0110     unsigned int    active;
0111     void __user *vdso;
0112 } mm_context_t;
0113
0114 /* patch sites */
0115 extern s32 patch__tlb_44x_hwater_D, patch__tlb_44x_hwater_I;
0116
0117 #endif /* !__ASSEMBLY__ */
0118
0119 #ifndef CONFIG_PPC_EARLY_DEBUG_44x
0120 #define PPC44x_EARLY_TLBS   1
0121 #else
0122 #define PPC44x_EARLY_TLBS   2
0123 #define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \
0124     | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
0125 #endif
0126
0127 /* Size of the TLBs used for pinning in lowmem */
0128 #define PPC_PIN_SIZE    (1 << 28)   /* 256M */
0129
0130 #if defined(CONFIG_PPC_4K_PAGES)
0131 #define PPC44x_TLBE_SIZE    PPC44x_TLB_4K
0132 #define PPC47x_TLBE_SIZE    PPC47x_TLB0_4K
0133 #define mmu_virtual_psize   MMU_PAGE_4K
0134 #elif defined(CONFIG_PPC_16K_PAGES)
0135 #define PPC44x_TLBE_SIZE    PPC44x_TLB_16K
0136 #define PPC47x_TLBE_SIZE    PPC47x_TLB0_16K
0137 #define mmu_virtual_psize   MMU_PAGE_16K
0138 #elif defined(CONFIG_PPC_64K_PAGES)
0139 #define PPC44x_TLBE_SIZE    PPC44x_TLB_64K
0140 #define PPC47x_TLBE_SIZE    PPC47x_TLB0_64K
0141 #define mmu_virtual_psize   MMU_PAGE_64K
0142 #elif defined(CONFIG_PPC_256K_PAGES)
0143 #define PPC44x_TLBE_SIZE    PPC44x_TLB_256K
0144 #define mmu_virtual_psize   MMU_PAGE_256K
0145 #else
0146 #error "Unsupported PAGE_SIZE"
0147 #endif
0148
0149 #define mmu_linear_psize    MMU_PAGE_256M
0150
0151 #define PPC44x_PGD_OFF_SHIFT    (32 - PGDIR_SHIFT + PGD_T_LOG2)
0152 #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2)
0153 #define PPC44x_PTE_ADD_SHIFT    (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2)
0154 #define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT)
0155
0156 #endif /* _ASM_POWERPC_MMU_44X_H_ */