nohash/32/mmu-40x.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_MMU_40X_H_
0003 #define _ASM_POWERPC_MMU_40X_H_
0004
0005 /*
0006  * PPC40x support
0007  */
0008
0009 #define PPC40X_TLB_SIZE 64
0010
0011 /*
0012  * TLB entries are defined by a "high" tag portion and a "low" data
0013  * portion.  On all architectures, the data portion is 32-bits.
0014  *
0015  * TLB entries are managed entirely under software control by reading,
0016  * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
0017  * instructions.
0018  */
0019
0020 #define TLB_LO          1
0021 #define TLB_HI          0
0022
0023 #define TLB_DATA        TLB_LO
0024 #define TLB_TAG         TLB_HI
0025
0026 /* Tag portion */
0027
0028 #define TLB_EPN_MASK    0xFFFFFC00      /* Effective Page Number */
0029 #define TLB_PAGESZ_MASK 0x00000380
0030 #define TLB_PAGESZ(x)   (((x) & 0x7) << 7)
0031 #define   PAGESZ_1K     0
0032 #define   PAGESZ_4K             1
0033 #define   PAGESZ_16K            2
0034 #define   PAGESZ_64K            3
0035 #define   PAGESZ_256K           4
0036 #define   PAGESZ_1M             5
0037 #define   PAGESZ_4M             6
0038 #define   PAGESZ_16M            7
0039 #define TLB_VALID       0x00000040      /* Entry is valid */
0040
0041 /* Data portion */
0042
0043 #define TLB_RPN_MASK    0xFFFFFC00      /* Real Page Number */
0044 #define TLB_PERM_MASK   0x00000300
0045 #define TLB_EX          0x00000200      /* Instruction execution allowed */
0046 #define TLB_WR          0x00000100      /* Writes permitted */
0047 #define TLB_ZSEL_MASK   0x000000F0
0048 #define TLB_ZSEL(x)     (((x) & 0xF) << 4)
0049 #define TLB_ATTR_MASK   0x0000000F
0050 #define TLB_W           0x00000008      /* Caching is write-through */
0051 #define TLB_I           0x00000004      /* Caching is inhibited */
0052 #define TLB_M           0x00000002      /* Memory is coherent */
0053 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
0054
0055 #ifndef __ASSEMBLY__
0056
0057 typedef struct {
0058     unsigned int    id;
0059     unsigned int    active;
0060     void __user *vdso;
0061 } mm_context_t;
0062
0063 #endif /* !__ASSEMBLY__ */
0064
0065 #define mmu_virtual_psize   MMU_PAGE_4K
0066 #define mmu_linear_psize    MMU_PAGE_256M
0067
0068 #endif /* _ASM_POWERPC_MMU_40X_H_ */