include/asm/mpic_msgr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
0004  */
0005
0006 #ifndef _ASM_MPIC_MSGR_H
0007 #define _ASM_MPIC_MSGR_H
0008
0009 #include <linux/types.h>
0010 #include <linux/spinlock.h>
0011 #include <asm/smp.h>
0012 #include <asm/io.h>
0013
0014 struct mpic_msgr {
0015     u32 __iomem *base;
0016     u32 __iomem *mer;
0017     int irq;
0018     unsigned char in_use;
0019     raw_spinlock_t lock;
0020     int num;
0021 };
0022
0023 /* Get a message register
0024  *
0025  * @reg_num:    the MPIC message register to get
0026  *
0027  * A pointer to the message register is returned.  If
0028  * the message register asked for is already in use, then
0029  * EBUSY is returned.  If the number given is not associated
0030  * with an actual message register, then ENODEV is returned.
0031  * Successfully getting the register marks it as in use.
0032  */
0033 extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
0034
0035 /* Relinquish a message register
0036  *
0037  * @msgr:   the message register to return
0038  *
0039  * Disables the given message register and marks it as free.
0040  * After this call has completed successully the message
0041  * register is available to be acquired by a call to
0042  * mpic_msgr_get.
0043  */
0044 extern void mpic_msgr_put(struct mpic_msgr *msgr);
0045
0046 /* Enable a message register
0047  *
0048  * @msgr:   the message register to enable
0049  *
0050  * The given message register is enabled for sending
0051  * messages.
0052  */
0053 extern void mpic_msgr_enable(struct mpic_msgr *msgr);
0054
0055 /* Disable a message register
0056  *
0057  * @msgr:   the message register to disable
0058  *
0059  * The given message register is disabled for sending
0060  * messages.
0061  */
0062 extern void mpic_msgr_disable(struct mpic_msgr *msgr);
0063
0064 /* Write a message to a message register
0065  *
0066  * @msgr:   the message register to write to
0067  * @message:    the message to write
0068  *
0069  * The given 32-bit message is written to the given message
0070  * register.  Writing to an enabled message registers fires
0071  * an interrupt.
0072  */
0073 static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
0074 {
0075     out_be32(msgr->base, message);
0076 }
0077
0078 /* Read a message from a message register
0079  *
0080  * @msgr:   the message register to read from
0081  *
0082  * Returns the 32-bit value currently in the given message register.
0083  * Upon reading the register any interrupts for that register are
0084  * cleared.
0085  */
0086 static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
0087 {
0088     return in_be32(msgr->base);
0089 }
0090
0091 /* Clear a message register
0092  *
0093  * @msgr:   the message register to clear
0094  *
0095  * Clears any interrupts associated with the given message register.
0096  */
0097 static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
0098 {
0099     (void) mpic_msgr_read(msgr);
0100 }
0101
0102 /* Set the destination CPU for the message register
0103  *
0104  * @msgr:   the message register whose destination is to be set
0105  * @cpu_num:    the Linux CPU number to bind the message register to
0106  *
0107  * Note that the CPU number given is the CPU number used by the kernel
0108  * and *not* the actual hardware CPU number.
0109  */
0110 static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
0111                          u32 cpu_num)
0112 {
0113     out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
0114 }
0115
0116 /* Get the IRQ number for the message register
0117  * @msgr:   the message register whose IRQ is to be returned
0118  *
0119  * Returns the IRQ number associated with the given message register.
0120  * 0 is returned if this message register is not capable of receiving
0121  * interrupts.  What message register can and cannot receive interrupts is
0122  * specified in the device tree for the system.
0123  */
0124 static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
0125 {
0126     return msgr->irq;
0127 }
0128
0129 #endif