include/asm/mpic.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_MPIC_H
0003 #define _ASM_POWERPC_MPIC_H
0004 #ifdef __KERNEL__
0005
0006 #include <linux/irq.h>
0007 #include <asm/dcr.h>
0008 #include <asm/msi_bitmap.h>
0009
0010 /*
0011  * Global registers
0012  */
0013
0014 #define MPIC_GREG_BASE          0x01000
0015
0016 #define MPIC_GREG_FEATURE_0     0x00000
0017 #define     MPIC_GREG_FEATURE_LAST_SRC_MASK     0x07ff0000
0018 #define     MPIC_GREG_FEATURE_LAST_SRC_SHIFT    16
0019 #define     MPIC_GREG_FEATURE_LAST_CPU_MASK     0x00001f00
0020 #define     MPIC_GREG_FEATURE_LAST_CPU_SHIFT    8
0021 #define     MPIC_GREG_FEATURE_VERSION_MASK      0xff
0022 #define MPIC_GREG_FEATURE_1     0x00010
0023 #define MPIC_GREG_GLOBAL_CONF_0     0x00020
0024 #define     MPIC_GREG_GCONF_RESET           0x80000000
0025 /* On the FSL mpic implementations the Mode field is expand to be
0026  * 2 bits wide:
0027  *  0b00 = pass through (interrupts routed to IRQ0)
0028  *  0b01 = Mixed mode
0029  *  0b10 = reserved
0030  *  0b11 = External proxy / coreint
0031  */
0032 #define     MPIC_GREG_GCONF_COREINT         0x60000000
0033 #define     MPIC_GREG_GCONF_8259_PTHROU_DIS     0x20000000
0034 #define     MPIC_GREG_GCONF_NO_BIAS         0x10000000
0035 #define     MPIC_GREG_GCONF_BASE_MASK       0x000fffff
0036 #define     MPIC_GREG_GCONF_MCK         0x08000000
0037 #define MPIC_GREG_GLOBAL_CONF_1     0x00030
0038 #define MPIC_GREG_VENDOR_0      0x00040
0039 #define MPIC_GREG_VENDOR_1      0x00050
0040 #define MPIC_GREG_VENDOR_2      0x00060
0041 #define MPIC_GREG_VENDOR_3      0x00070
0042 #define MPIC_GREG_VENDOR_ID     0x00080
0043 #define     MPIC_GREG_VENDOR_ID_STEPPING_MASK   0x00ff0000
0044 #define     MPIC_GREG_VENDOR_ID_STEPPING_SHIFT  16
0045 #define     MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK  0x0000ff00
0046 #define     MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
0047 #define     MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK  0x000000ff
0048 #define MPIC_GREG_PROCESSOR_INIT    0x00090
0049 #define MPIC_GREG_IPI_VECTOR_PRI_0  0x000a0
0050 #define MPIC_GREG_IPI_VECTOR_PRI_1  0x000b0
0051 #define MPIC_GREG_IPI_VECTOR_PRI_2  0x000c0
0052 #define MPIC_GREG_IPI_VECTOR_PRI_3  0x000d0
0053 #define MPIC_GREG_IPI_STRIDE        0x10
0054 #define MPIC_GREG_SPURIOUS      0x000e0
0055 #define MPIC_GREG_TIMER_FREQ        0x000f0
0056
0057 /*
0058  *
0059  * Timer registers
0060  */
0061 #define MPIC_TIMER_BASE         0x01100
0062 #define MPIC_TIMER_STRIDE       0x40
0063 #define MPIC_TIMER_GROUP_STRIDE     0x1000
0064
0065 #define MPIC_TIMER_CURRENT_CNT      0x00000
0066 #define MPIC_TIMER_BASE_CNT     0x00010
0067 #define MPIC_TIMER_VECTOR_PRI       0x00020
0068 #define MPIC_TIMER_DESTINATION      0x00030
0069
0070 /*
0071  * Per-Processor registers
0072  */
0073
0074 #define MPIC_CPU_THISBASE       0x00000
0075 #define MPIC_CPU_BASE           0x20000
0076 #define MPIC_CPU_STRIDE         0x01000
0077
0078 #define MPIC_CPU_IPI_DISPATCH_0     0x00040
0079 #define MPIC_CPU_IPI_DISPATCH_1     0x00050
0080 #define MPIC_CPU_IPI_DISPATCH_2     0x00060
0081 #define MPIC_CPU_IPI_DISPATCH_3     0x00070
0082 #define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
0083 #define MPIC_CPU_CURRENT_TASK_PRI   0x00080
0084 #define     MPIC_CPU_TASKPRI_MASK           0x0000000f
0085 #define MPIC_CPU_WHOAMI         0x00090
0086 #define     MPIC_CPU_WHOAMI_MASK            0x0000001f
0087 #define MPIC_CPU_INTACK         0x000a0
0088 #define MPIC_CPU_EOI            0x000b0
0089 #define MPIC_CPU_MCACK          0x000c0
0090
0091 /*
0092  * Per-source registers
0093  */
0094
0095 #define MPIC_IRQ_BASE           0x10000
0096 #define MPIC_IRQ_STRIDE         0x00020
0097 #define MPIC_IRQ_VECTOR_PRI     0x00000
0098 #define     MPIC_VECPRI_MASK            0x80000000
0099 #define     MPIC_VECPRI_ACTIVITY            0x40000000  /* Read Only */
0100 #define     MPIC_VECPRI_PRIORITY_MASK       0x000f0000
0101 #define     MPIC_VECPRI_PRIORITY_SHIFT      16
0102 #define     MPIC_VECPRI_VECTOR_MASK         0x000007ff
0103 #define     MPIC_VECPRI_POLARITY_POSITIVE       0x00800000
0104 #define     MPIC_VECPRI_POLARITY_NEGATIVE       0x00000000
0105 #define     MPIC_VECPRI_POLARITY_MASK       0x00800000
0106 #define     MPIC_VECPRI_SENSE_LEVEL         0x00400000
0107 #define     MPIC_VECPRI_SENSE_EDGE          0x00000000
0108 #define     MPIC_VECPRI_SENSE_MASK          0x00400000
0109 #define MPIC_IRQ_DESTINATION        0x00010
0110
0111 #define MPIC_FSL_BRR1           0x00000
0112 #define     MPIC_FSL_BRR1_VER           0x0000ffff
0113
0114 #define MPIC_MAX_IRQ_SOURCES    2048
0115 #define MPIC_MAX_CPUS       32
0116 #define MPIC_MAX_ISU        32
0117
0118 #define MPIC_MAX_ERR      32
0119 #define MPIC_FSL_ERR_INT  16
0120
0121 /*
0122  * Tsi108 implementation of MPIC has many differences from the original one
0123  */
0124
0125 /*
0126  * Global registers
0127  */
0128
0129 #define TSI108_GREG_BASE        0x00000
0130 #define TSI108_GREG_FEATURE_0       0x00000
0131 #define TSI108_GREG_GLOBAL_CONF_0   0x00004
0132 #define TSI108_GREG_VENDOR_ID       0x0000c
0133 #define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204     /* Doorbell 0 */
0134 #define TSI108_GREG_IPI_STRIDE      0x0c
0135 #define TSI108_GREG_SPURIOUS        0x00010
0136 #define TSI108_GREG_TIMER_FREQ      0x00014
0137
0138 /*
0139  * Timer registers
0140  */
0141 #define TSI108_TIMER_BASE       0x0030
0142 #define TSI108_TIMER_STRIDE     0x10
0143 #define TSI108_TIMER_CURRENT_CNT    0x00000
0144 #define TSI108_TIMER_BASE_CNT       0x00004
0145 #define TSI108_TIMER_VECTOR_PRI     0x00008
0146 #define TSI108_TIMER_DESTINATION    0x0000c
0147
0148 /*
0149  * Per-Processor registers
0150  */
0151 #define TSI108_CPU_BASE         0x00300
0152 #define TSI108_CPU_STRIDE       0x00040
0153 #define TSI108_CPU_IPI_DISPATCH_0   0x00200
0154 #define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
0155 #define TSI108_CPU_CURRENT_TASK_PRI 0x00000
0156 #define TSI108_CPU_WHOAMI       0xffffffff
0157 #define TSI108_CPU_INTACK       0x00004
0158 #define TSI108_CPU_EOI          0x00008
0159 #define TSI108_CPU_MCACK        0x00004 /* Doesn't really exist here */
0160
0161 /*
0162  * Per-source registers
0163  */
0164 #define TSI108_IRQ_BASE         0x00100
0165 #define TSI108_IRQ_STRIDE       0x00008
0166 #define TSI108_IRQ_VECTOR_PRI       0x00000
0167 #define TSI108_VECPRI_VECTOR_MASK   0x000000ff
0168 #define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
0169 #define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
0170 #define TSI108_VECPRI_SENSE_LEVEL   0x02000000
0171 #define TSI108_VECPRI_SENSE_EDGE    0x00000000
0172 #define TSI108_VECPRI_POLARITY_MASK 0x01000000
0173 #define TSI108_VECPRI_SENSE_MASK    0x02000000
0174 #define TSI108_IRQ_DESTINATION      0x00004
0175
0176 /* weird mpic register indices and mask bits in the HW info array */
0177 enum {
0178     MPIC_IDX_GREG_BASE = 0,
0179     MPIC_IDX_GREG_FEATURE_0,
0180     MPIC_IDX_GREG_GLOBAL_CONF_0,
0181     MPIC_IDX_GREG_VENDOR_ID,
0182     MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
0183     MPIC_IDX_GREG_IPI_STRIDE,
0184     MPIC_IDX_GREG_SPURIOUS,
0185     MPIC_IDX_GREG_TIMER_FREQ,
0186
0187     MPIC_IDX_TIMER_BASE,
0188     MPIC_IDX_TIMER_STRIDE,
0189     MPIC_IDX_TIMER_CURRENT_CNT,
0190     MPIC_IDX_TIMER_BASE_CNT,
0191     MPIC_IDX_TIMER_VECTOR_PRI,
0192     MPIC_IDX_TIMER_DESTINATION,
0193
0194     MPIC_IDX_CPU_BASE,
0195     MPIC_IDX_CPU_STRIDE,
0196     MPIC_IDX_CPU_IPI_DISPATCH_0,
0197     MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
0198     MPIC_IDX_CPU_CURRENT_TASK_PRI,
0199     MPIC_IDX_CPU_WHOAMI,
0200     MPIC_IDX_CPU_INTACK,
0201     MPIC_IDX_CPU_EOI,
0202     MPIC_IDX_CPU_MCACK,
0203
0204     MPIC_IDX_IRQ_BASE,
0205     MPIC_IDX_IRQ_STRIDE,
0206     MPIC_IDX_IRQ_VECTOR_PRI,
0207
0208     MPIC_IDX_VECPRI_VECTOR_MASK,
0209     MPIC_IDX_VECPRI_POLARITY_POSITIVE,
0210     MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
0211     MPIC_IDX_VECPRI_SENSE_LEVEL,
0212     MPIC_IDX_VECPRI_SENSE_EDGE,
0213     MPIC_IDX_VECPRI_POLARITY_MASK,
0214     MPIC_IDX_VECPRI_SENSE_MASK,
0215     MPIC_IDX_IRQ_DESTINATION,
0216     MPIC_IDX_END
0217 };
0218
0219
0220 #ifdef CONFIG_MPIC_U3_HT_IRQS
0221 /* Fixup table entry */
0222 struct mpic_irq_fixup
0223 {
0224     u8 __iomem  *base;
0225     u8 __iomem  *applebase;
0226     u32     data;
0227     unsigned int    index;
0228 };
0229 #endif /* CONFIG_MPIC_U3_HT_IRQS */
0230
0231
0232 enum mpic_reg_type {
0233     mpic_access_mmio_le,
0234     mpic_access_mmio_be,
0235 #ifdef CONFIG_PPC_DCR
0236     mpic_access_dcr
0237 #endif
0238 };
0239
0240 struct mpic_reg_bank {
0241     u32 __iomem *base;
0242 #ifdef CONFIG_PPC_DCR
0243     dcr_host_t  dhost;
0244 #endif /* CONFIG_PPC_DCR */
0245 };
0246
0247 struct mpic_irq_save {
0248     u32     vecprio,
0249             dest;
0250 #ifdef CONFIG_MPIC_U3_HT_IRQS
0251     u32     fixup_data;
0252 #endif
0253 };
0254
0255 /* The instance data of a given MPIC */
0256 struct mpic
0257 {
0258     /* The OpenFirmware dt node for this MPIC */
0259     struct device_node *node;
0260
0261     /* The remapper for this MPIC */
0262     struct irq_domain   *irqhost;
0263
0264     /* The "linux" controller struct */
0265     struct irq_chip     hc_irq;
0266 #ifdef CONFIG_MPIC_U3_HT_IRQS
0267     struct irq_chip     hc_ht_irq;
0268 #endif
0269 #ifdef CONFIG_SMP
0270     struct irq_chip     hc_ipi;
0271 #endif
0272     struct irq_chip     hc_tm;
0273     struct irq_chip     hc_err;
0274     const char      *name;
0275     /* Flags */
0276     unsigned int        flags;
0277     /* How many irq sources in a given ISU */
0278     unsigned int        isu_size;
0279     unsigned int        isu_shift;
0280     unsigned int        isu_mask;
0281     /* Number of sources */
0282     unsigned int        num_sources;
0283
0284     /* vector numbers used for internal sources (ipi/timers) */
0285     unsigned int        ipi_vecs[4];
0286     unsigned int        timer_vecs[8];
0287     /* vector numbers used for FSL MPIC error interrupts */
0288     unsigned int        err_int_vecs[MPIC_MAX_ERR];
0289
0290     /* Spurious vector to program into unused sources */
0291     unsigned int        spurious_vec;
0292
0293 #ifdef CONFIG_MPIC_U3_HT_IRQS
0294     /* The fixup table */
0295     struct mpic_irq_fixup   *fixups;
0296     raw_spinlock_t  fixup_lock;
0297 #endif
0298
0299     /* Register access method */
0300     enum mpic_reg_type  reg_type;
0301
0302     /* The physical base address of the MPIC */
0303     phys_addr_t paddr;
0304
0305     /* The various ioremap'ed bases */
0306     struct mpic_reg_bank    thiscpuregs;
0307     struct mpic_reg_bank    gregs;
0308     struct mpic_reg_bank    tmregs;
0309     struct mpic_reg_bank    cpuregs[MPIC_MAX_CPUS];
0310     struct mpic_reg_bank    isus[MPIC_MAX_ISU];
0311
0312     /* ioremap'ed base for error interrupt registers */
0313     u32 __iomem *err_regs;
0314
0315     /* Protected sources */
0316     unsigned long       *protected;
0317
0318 #ifdef CONFIG_MPIC_WEIRD
0319     /* Pointer to HW info array */
0320     u32         *hw_set;
0321 #endif
0322
0323 #ifdef CONFIG_PCI_MSI
0324     struct msi_bitmap   msi_bitmap;
0325 #endif
0326
0327 #ifdef CONFIG_MPIC_BROKEN_REGREAD
0328     u32         isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
0329 #endif
0330
0331     /* link */
0332     struct mpic     *next;
0333
0334 #ifdef CONFIG_PM
0335     struct mpic_irq_save    *save_data;
0336 #endif
0337 };
0338
0339 extern struct bus_type mpic_subsys;
0340
0341 /*
0342  * MPIC flags (passed to mpic_alloc)
0343  *
0344  * The top 4 bits contain an MPIC bhw id that is used to index the
0345  * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
0346  * Note setting any ID (leaving those bits to 0) means standard MPIC
0347  */
0348
0349 /*
0350  * This is a secondary ("chained") controller; it only uses the CPU0
0351  * registers.  Primary controllers have IPIs and affinity control.
0352  */
0353 #define MPIC_SECONDARY          0x00000001
0354
0355 /* Set this for a big-endian MPIC */
0356 #define MPIC_BIG_ENDIAN         0x00000002
0357 /* Broken U3 MPIC */
0358 #define MPIC_U3_HT_IRQS         0x00000004
0359 /* Broken IPI registers (autodetected) */
0360 #define MPIC_BROKEN_IPI         0x00000008
0361 /* Spurious vector requires EOI */
0362 #define MPIC_SPV_EOI            0x00000020
0363 /* No passthrough disable */
0364 #define MPIC_NO_PTHROU_DIS      0x00000040
0365 /* DCR based MPIC */
0366 #define MPIC_USES_DCR           0x00000080
0367 /* MPIC has 11-bit vector fields (or larger) */
0368 #define MPIC_LARGE_VECTORS      0x00000100
0369 /* Enable delivery of prio 15 interrupts as MCK instead of EE */
0370 #define MPIC_ENABLE_MCK         0x00000200
0371 /* Disable bias among target selection, spread interrupts evenly */
0372 #define MPIC_NO_BIAS            0x00000400
0373 /* Destination only supports a single CPU at a time */
0374 #define MPIC_SINGLE_DEST_CPU        0x00001000
0375 /* Enable CoreInt delivery of interrupts */
0376 #define MPIC_ENABLE_COREINT     0x00002000
0377 /* Do not reset the MPIC during initialization */
0378 #define MPIC_NO_RESET           0x00004000
0379 /* Freescale MPIC (compatible includes "fsl,mpic") */
0380 #define MPIC_FSL            0x00008000
0381 /* Freescale MPIC supports EIMR (error interrupt mask register).
0382  * This flag is set for MPIC version >= 4.1 (version determined
0383  * from the BRR1 register).
0384 */
0385 #define MPIC_FSL_HAS_EIMR       0x00010000
0386
0387 /* MPIC HW modification ID */
0388 #define MPIC_REGSET_MASK        0xf0000000
0389 #define MPIC_REGSET(val)        (((val) & 0xf ) << 28)
0390 #define MPIC_GET_REGSET(flags)      (((flags) >> 28) & 0xf)
0391
0392 #define MPIC_REGSET_STANDARD        MPIC_REGSET(0)  /* Original MPIC */
0393 #define MPIC_REGSET_TSI108      MPIC_REGSET(1)  /* Tsi108/109 PIC */
0394
0395 /* Get the version of primary MPIC */
0396 #ifdef CONFIG_MPIC
0397 extern u32 fsl_mpic_primary_get_version(void);
0398 #else
0399 static inline u32 fsl_mpic_primary_get_version(void)
0400 {
0401     return 0;
0402 }
0403 #endif
0404
0405 /* Allocate the controller structure and setup the linux irq descs
0406  * for the range if interrupts passed in. No HW initialization is
0407  * actually performed.
0408  *
0409  * @phys_addr:  physial base address of the MPIC
0410  * @flags:  flags, see constants above
0411  * @isu_size:   number of interrupts in an ISU. Use 0 to use a
0412  *              standard ISU-less setup (aka powermac)
0413  * @irq_offset: first irq number to assign to this mpic
0414  * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
0415  *          to match the number of sources
0416  * @ipi_offset: first irq number to assign to this mpic IPI sources,
0417  *      used only on primary mpic
0418  * @senses: array of sense values
0419  * @senses_num: number of entries in the array
0420  *
0421  * Note about the sense array. If none is passed, all interrupts are
0422  * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
0423  * case they are edge positive (and the array is ignored anyway).
0424  * The values in the array start at the first source of the MPIC,
0425  * that is senses[0] correspond to linux irq "irq_offset".
0426  */
0427 extern struct mpic *mpic_alloc(struct device_node *node,
0428                    phys_addr_t phys_addr,
0429                    unsigned int flags,
0430                    unsigned int isu_size,
0431                    unsigned int irq_count,
0432                    const char *name);
0433
0434 /* Assign ISUs, to call before mpic_init()
0435  *
0436  * @mpic:   controller structure as returned by mpic_alloc()
0437  * @isu_num:    ISU number
0438  * @phys_addr:  physical address of the ISU
0439  */
0440 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
0441                 phys_addr_t phys_addr);
0442
0443
0444 /* Initialize the controller. After this has been called, none of the above
0445  * should be called again for this mpic
0446  */
0447 extern void mpic_init(struct mpic *mpic);
0448
0449 /*
0450  * All of the following functions must only be used after the
0451  * ISUs have been assigned and the controller fully initialized
0452  * with mpic_init()
0453  */
0454
0455
0456 /* Change the priority of an interrupt. Default is 8 for irqs and
0457  * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
0458  * IPI number is then the offset'ed (linux irq number mapped to the IPI)
0459  */
0460 extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
0461
0462 /* Setup a non-boot CPU */
0463 extern void mpic_setup_this_cpu(void);
0464
0465 /* Clean up for kexec (or cpu offline or ...) */
0466 extern void mpic_teardown_this_cpu(int secondary);
0467
0468 /* Get the current cpu priority for this cpu (0..15) */
0469 extern int mpic_cpu_get_priority(void);
0470
0471 /* Set the current cpu priority for this cpu */
0472 extern void mpic_cpu_set_priority(int prio);
0473
0474 /* Request IPIs on primary mpic */
0475 void __init mpic_request_ipis(void);
0476
0477 /* Send a message (IPI) to a given target (cpu number or MSG_*) */
0478 void smp_mpic_message_pass(int target, int msg);
0479
0480 /* Unmask a specific virq */
0481 extern void mpic_unmask_irq(struct irq_data *d);
0482 /* Mask a specific virq */
0483 extern void mpic_mask_irq(struct irq_data *d);
0484 /* EOI a specific virq */
0485 extern void mpic_end_irq(struct irq_data *d);
0486
0487 /* Fetch interrupt from a given mpic */
0488 extern unsigned int mpic_get_one_irq(struct mpic *mpic);
0489 /* This one gets from the primary mpic */
0490 extern unsigned int mpic_get_irq(void);
0491 /* This one gets from the primary mpic via CoreInt*/
0492 extern unsigned int mpic_get_coreint_irq(void);
0493 /* Fetch Machine Check interrupt from primary mpic */
0494 extern unsigned int mpic_get_mcirq(void);
0495
0496 #endif /* __KERNEL__ */
0497 #endif  /* _ASM_POWERPC_MPIC_H */