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0001 /*
0002  * include/asm-ppc/mpc52xx_psc.h
0003  *
0004  * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
0005  * PSCs. Theses are shared between multiple drivers since a PSC can be
0006  * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
0007  *
0008  *
0009  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
0010  *
0011  * Based/Extracted from some header of the 2.4 originally written by
0012  * Dale Farnsworth <dfarnsworth@mvista.com>
0013  *
0014  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
0015  * Copyright (C) 2003 MontaVista, Software, Inc.
0016  *
0017  * This file is licensed under the terms of the GNU General Public License
0018  * version 2. This program is licensed "as is" without any warranty of any
0019  * kind, whether express or implied.
0020  */
0021 
0022 #ifndef __ASM_MPC52xx_PSC_H__
0023 #define __ASM_MPC52xx_PSC_H__
0024 
0025 #include <asm/types.h>
0026 
0027 /* Max number of PSCs */
0028 #ifdef CONFIG_PPC_MPC512x
0029 #define MPC52xx_PSC_MAXNUM     12
0030 #else
0031 #define MPC52xx_PSC_MAXNUM  6
0032 #endif
0033 
0034 /* Programmable Serial Controller (PSC) status register bits */
0035 #define MPC52xx_PSC_SR_UNEX_RX  0x0001
0036 #define MPC52xx_PSC_SR_DATA_VAL 0x0002
0037 #define MPC52xx_PSC_SR_DATA_OVR 0x0004
0038 #define MPC52xx_PSC_SR_CMDSEND  0x0008
0039 #define MPC52xx_PSC_SR_CDE  0x0080
0040 #define MPC52xx_PSC_SR_RXRDY    0x0100
0041 #define MPC52xx_PSC_SR_RXFULL   0x0200
0042 #define MPC52xx_PSC_SR_TXRDY    0x0400
0043 #define MPC52xx_PSC_SR_TXEMP    0x0800
0044 #define MPC52xx_PSC_SR_OE   0x1000
0045 #define MPC52xx_PSC_SR_PE   0x2000
0046 #define MPC52xx_PSC_SR_FE   0x4000
0047 #define MPC52xx_PSC_SR_RB   0x8000
0048 
0049 /* PSC Command values */
0050 #define MPC52xx_PSC_RX_ENABLE       0x0001
0051 #define MPC52xx_PSC_RX_DISABLE      0x0002
0052 #define MPC52xx_PSC_TX_ENABLE       0x0004
0053 #define MPC52xx_PSC_TX_DISABLE      0x0008
0054 #define MPC52xx_PSC_SEL_MODE_REG_1  0x0010
0055 #define MPC52xx_PSC_RST_RX      0x0020
0056 #define MPC52xx_PSC_RST_TX      0x0030
0057 #define MPC52xx_PSC_RST_ERR_STAT    0x0040
0058 #define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
0059 #define MPC52xx_PSC_START_BRK       0x0060
0060 #define MPC52xx_PSC_STOP_BRK        0x0070
0061 
0062 /* PSC TxRx FIFO status bits */
0063 #define MPC52xx_PSC_RXTX_FIFO_ERR   0x0040
0064 #define MPC52xx_PSC_RXTX_FIFO_UF    0x0020
0065 #define MPC52xx_PSC_RXTX_FIFO_OF    0x0010
0066 #define MPC52xx_PSC_RXTX_FIFO_FR    0x0008
0067 #define MPC52xx_PSC_RXTX_FIFO_FULL  0x0004
0068 #define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
0069 #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
0070 
0071 /* PSC interrupt status/mask bits */
0072 #define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001
0073 #define MPC52xx_PSC_IMR_DATA_VALID  0x0002
0074 #define MPC52xx_PSC_IMR_DATA_OVR    0x0004
0075 #define MPC52xx_PSC_IMR_CMD_SEND    0x0008
0076 #define MPC52xx_PSC_IMR_ERROR       0x0040
0077 #define MPC52xx_PSC_IMR_DEOF        0x0080
0078 #define MPC52xx_PSC_IMR_TXRDY       0x0100
0079 #define MPC52xx_PSC_IMR_RXRDY       0x0200
0080 #define MPC52xx_PSC_IMR_DB      0x0400
0081 #define MPC52xx_PSC_IMR_TXEMP       0x0800
0082 #define MPC52xx_PSC_IMR_ORERR       0x1000
0083 #define MPC52xx_PSC_IMR_IPC     0x8000
0084 
0085 /* PSC input port change bits */
0086 #define MPC52xx_PSC_CTS         0x01
0087 #define MPC52xx_PSC_DCD         0x02
0088 #define MPC52xx_PSC_D_CTS       0x10
0089 #define MPC52xx_PSC_D_DCD       0x20
0090 
0091 /* PSC acr bits */
0092 #define MPC52xx_PSC_IEC_CTS     0x01
0093 #define MPC52xx_PSC_IEC_DCD     0x02
0094 
0095 /* PSC output port bits */
0096 #define MPC52xx_PSC_OP_RTS      0x01
0097 #define MPC52xx_PSC_OP_RES      0x02
0098 
0099 /* PSC mode fields */
0100 #define MPC52xx_PSC_MODE_5_BITS         0x00
0101 #define MPC52xx_PSC_MODE_6_BITS         0x01
0102 #define MPC52xx_PSC_MODE_7_BITS         0x02
0103 #define MPC52xx_PSC_MODE_8_BITS         0x03
0104 #define MPC52xx_PSC_MODE_BITS_MASK      0x03
0105 #define MPC52xx_PSC_MODE_PAREVEN        0x00
0106 #define MPC52xx_PSC_MODE_PARODD         0x04
0107 #define MPC52xx_PSC_MODE_PARFORCE       0x08
0108 #define MPC52xx_PSC_MODE_PARNONE        0x10
0109 #define MPC52xx_PSC_MODE_ERR            0x20
0110 #define MPC52xx_PSC_MODE_FFULL          0x40
0111 #define MPC52xx_PSC_MODE_RXRTS          0x80
0112 
0113 #define MPC52xx_PSC_MODE_ONE_STOP_5_BITS    0x00
0114 #define MPC52xx_PSC_MODE_ONE_STOP       0x07
0115 #define MPC52xx_PSC_MODE_TWO_STOP       0x0f
0116 #define MPC52xx_PSC_MODE_TXCTS          0x10
0117 
0118 #define MPC52xx_PSC_RFNUM_MASK  0x01ff
0119 
0120 #define MPC52xx_PSC_SICR_DTS1           (1 << 29)
0121 #define MPC52xx_PSC_SICR_SHDR           (1 << 28)
0122 #define MPC52xx_PSC_SICR_SIM_MASK       (0xf << 24)
0123 #define MPC52xx_PSC_SICR_SIM_UART       (0x0 << 24)
0124 #define MPC52xx_PSC_SICR_SIM_UART_DCD       (0x8 << 24)
0125 #define MPC52xx_PSC_SICR_SIM_CODEC_8        (0x1 << 24)
0126 #define MPC52xx_PSC_SICR_SIM_CODEC_16       (0x2 << 24)
0127 #define MPC52xx_PSC_SICR_SIM_AC97       (0x3 << 24)
0128 #define MPC52xx_PSC_SICR_SIM_SIR        (0x8 << 24)
0129 #define MPC52xx_PSC_SICR_SIM_SIR_DCD        (0xc << 24)
0130 #define MPC52xx_PSC_SICR_SIM_MIR        (0x5 << 24)
0131 #define MPC52xx_PSC_SICR_SIM_FIR        (0x6 << 24)
0132 #define MPC52xx_PSC_SICR_SIM_CODEC_24       (0x7 << 24)
0133 #define MPC52xx_PSC_SICR_SIM_CODEC_32       (0xf << 24)
0134 #define MPC52xx_PSC_SICR_ACRB           (0x8 << 24)
0135 #define MPC52xx_PSC_SICR_AWR            (1 << 30)
0136 #define MPC52xx_PSC_SICR_GENCLK         (1 << 23)
0137 #define MPC52xx_PSC_SICR_I2S            (1 << 22)
0138 #define MPC52xx_PSC_SICR_CLKPOL         (1 << 21)
0139 #define MPC52xx_PSC_SICR_SYNCPOL        (1 << 20)
0140 #define MPC52xx_PSC_SICR_CELLSLAVE      (1 << 19)
0141 #define MPC52xx_PSC_SICR_CELL2XCLK      (1 << 18)
0142 #define MPC52xx_PSC_SICR_ESAI           (1 << 17)
0143 #define MPC52xx_PSC_SICR_ENAC97         (1 << 16)
0144 #define MPC52xx_PSC_SICR_SPI            (1 << 15)
0145 #define MPC52xx_PSC_SICR_MSTR           (1 << 14)
0146 #define MPC52xx_PSC_SICR_CPOL           (1 << 13)
0147 #define MPC52xx_PSC_SICR_CPHA           (1 << 12)
0148 #define MPC52xx_PSC_SICR_USEEOF         (1 << 11)
0149 #define MPC52xx_PSC_SICR_DISABLEEOF     (1 << 10)
0150 
0151 /* Structure of the hardware registers */
0152 struct mpc52xx_psc {
0153     union {
0154         u8  mode;       /* PSC + 0x00 */
0155         u8  mr2;
0156     };
0157     u8      reserved0[3];
0158     union {             /* PSC + 0x04 */
0159         u16 status;
0160         u16 clock_select;
0161     } sr_csr;
0162 #define mpc52xx_psc_status  sr_csr.status
0163 #define mpc52xx_psc_clock_select sr_csr.clock_select
0164     u16     reserved1;
0165     u8      command;    /* PSC + 0x08 */
0166     u8      reserved2[3];
0167     union {             /* PSC + 0x0c */
0168         u8  buffer_8;
0169         u16 buffer_16;
0170         u32 buffer_32;
0171     } buffer;
0172 #define mpc52xx_psc_buffer_8    buffer.buffer_8
0173 #define mpc52xx_psc_buffer_16   buffer.buffer_16
0174 #define mpc52xx_psc_buffer_32   buffer.buffer_32
0175     union {             /* PSC + 0x10 */
0176         u8  ipcr;
0177         u8  acr;
0178     } ipcr_acr;
0179 #define mpc52xx_psc_ipcr    ipcr_acr.ipcr
0180 #define mpc52xx_psc_acr     ipcr_acr.acr
0181     u8      reserved3[3];
0182     union {             /* PSC + 0x14 */
0183         u16 isr;
0184         u16 imr;
0185     } isr_imr;
0186 #define mpc52xx_psc_isr     isr_imr.isr
0187 #define mpc52xx_psc_imr     isr_imr.imr
0188     u16     reserved4;
0189     u8      ctur;       /* PSC + 0x18 */
0190     u8      reserved5[3];
0191     u8      ctlr;       /* PSC + 0x1c */
0192     u8      reserved6[3];
0193     /* BitClkDiv field of CCR is byte swapped in
0194      * the hardware for mpc5200/b compatibility */
0195     u32     ccr;        /* PSC + 0x20 */
0196     u32     ac97_slots; /* PSC + 0x24 */
0197     u32     ac97_cmd;   /* PSC + 0x28 */
0198     u32     ac97_data;  /* PSC + 0x2c */
0199     u8      ivr;        /* PSC + 0x30 */
0200     u8      reserved8[3];
0201     u8      ip;     /* PSC + 0x34 */
0202     u8      reserved9[3];
0203     u8      op1;        /* PSC + 0x38 */
0204     u8      reserved10[3];
0205     u8      op0;        /* PSC + 0x3c */
0206     u8      reserved11[3];
0207     u32     sicr;       /* PSC + 0x40 */
0208     u8      ircr1;      /* PSC + 0x44 */
0209     u8      reserved13[3];
0210     u8      ircr2;      /* PSC + 0x44 */
0211     u8      reserved14[3];
0212     u8      irsdr;      /* PSC + 0x4c */
0213     u8      reserved15[3];
0214     u8      irmdr;      /* PSC + 0x50 */
0215     u8      reserved16[3];
0216     u8      irfdr;      /* PSC + 0x54 */
0217     u8      reserved17[3];
0218 };
0219 
0220 struct mpc52xx_psc_fifo {
0221     u16     rfnum;      /* PSC + 0x58 */
0222     u16     reserved18;
0223     u16     tfnum;      /* PSC + 0x5c */
0224     u16     reserved19;
0225     u32     rfdata;     /* PSC + 0x60 */
0226     u16     rfstat;     /* PSC + 0x64 */
0227     u16     reserved20;
0228     u8      rfcntl;     /* PSC + 0x68 */
0229     u8      reserved21[5];
0230     u16     rfalarm;    /* PSC + 0x6e */
0231     u16     reserved22;
0232     u16     rfrptr;     /* PSC + 0x72 */
0233     u16     reserved23;
0234     u16     rfwptr;     /* PSC + 0x76 */
0235     u16     reserved24;
0236     u16     rflrfptr;   /* PSC + 0x7a */
0237     u16     reserved25;
0238     u16     rflwfptr;   /* PSC + 0x7e */
0239     u32     tfdata;     /* PSC + 0x80 */
0240     u16     tfstat;     /* PSC + 0x84 */
0241     u16     reserved26;
0242     u8      tfcntl;     /* PSC + 0x88 */
0243     u8      reserved27[5];
0244     u16     tfalarm;    /* PSC + 0x8e */
0245     u16     reserved28;
0246     u16     tfrptr;     /* PSC + 0x92 */
0247     u16     reserved29;
0248     u16     tfwptr;     /* PSC + 0x96 */
0249     u16     reserved30;
0250     u16     tflrfptr;   /* PSC + 0x9a */
0251     u16     reserved31;
0252     u16     tflwfptr;   /* PSC + 0x9e */
0253 };
0254 
0255 #define MPC512x_PSC_FIFO_EOF        0x100
0256 #define MPC512x_PSC_FIFO_RESET_SLICE    0x80
0257 #define MPC512x_PSC_FIFO_ENABLE_SLICE   0x01
0258 #define MPC512x_PSC_FIFO_ENABLE_DMA 0x04
0259 
0260 #define MPC512x_PSC_FIFO_EMPTY      0x1
0261 #define MPC512x_PSC_FIFO_FULL       0x2
0262 #define MPC512x_PSC_FIFO_ALARM      0x4
0263 #define MPC512x_PSC_FIFO_URERR      0x8
0264 
0265 struct mpc512x_psc_fifo {
0266     u32     reserved1[10];
0267     u32     txcmd;      /* PSC + 0x80 */
0268     u32     txalarm;    /* PSC + 0x84 */
0269     u32     txsr;       /* PSC + 0x88 */
0270     u32     txisr;      /* PSC + 0x8c */
0271     u32     tximr;      /* PSC + 0x90 */
0272     u32     txcnt;      /* PSC + 0x94 */
0273     u32     txptr;      /* PSC + 0x98 */
0274     u32     txsz;       /* PSC + 0x9c */
0275     u32     reserved2[7];
0276     union {
0277         u8  txdata_8;
0278         u16 txdata_16;
0279         u32 txdata_32;
0280     } txdata;           /* PSC + 0xbc */
0281 #define txdata_8 txdata.txdata_8
0282 #define txdata_16 txdata.txdata_16
0283 #define txdata_32 txdata.txdata_32
0284     u32     rxcmd;      /* PSC + 0xc0 */
0285     u32     rxalarm;    /* PSC + 0xc4 */
0286     u32     rxsr;       /* PSC + 0xc8 */
0287     u32     rxisr;      /* PSC + 0xcc */
0288     u32     rximr;      /* PSC + 0xd0 */
0289     u32     rxcnt;      /* PSC + 0xd4 */
0290     u32     rxptr;      /* PSC + 0xd8 */
0291     u32     rxsz;       /* PSC + 0xdc */
0292     u32     reserved3[7];
0293     union {
0294         u8  rxdata_8;
0295         u16 rxdata_16;
0296         u32 rxdata_32;
0297     } rxdata;           /* PSC + 0xfc */
0298 #define rxdata_8 rxdata.rxdata_8
0299 #define rxdata_16 rxdata.rxdata_16
0300 #define rxdata_32 rxdata.rxdata_32
0301 };
0302 
0303 struct mpc5125_psc {
0304     u8      mr1;            /* PSC + 0x00 */
0305     u8      reserved0[3];
0306     u8      mr2;            /* PSC + 0x04 */
0307     u8      reserved1[3];
0308     struct {
0309         u16     status;     /* PSC + 0x08 */
0310         u8      reserved2[2];
0311         u8      clock_select;   /* PSC + 0x0c */
0312         u8      reserved3[3];
0313     } sr_csr;
0314     u8      command;        /* PSC + 0x10 */
0315     u8      reserved4[3];
0316     union {                 /* PSC + 0x14 */
0317         u8      buffer_8;
0318         u16     buffer_16;
0319         u32     buffer_32;
0320     } buffer;
0321     struct {
0322         u8      ipcr;       /* PSC + 0x18 */
0323         u8      reserved5[3];
0324         u8      acr;        /* PSC + 0x1c */
0325         u8      reserved6[3];
0326     } ipcr_acr;
0327     struct {
0328         u16     isr;        /* PSC + 0x20 */
0329         u8      reserved7[2];
0330         u16     imr;        /* PSC + 0x24 */
0331         u8      reserved8[2];
0332     } isr_imr;
0333     u8      ctur;           /* PSC + 0x28 */
0334     u8      reserved9[3];
0335     u8      ctlr;           /* PSC + 0x2c */
0336     u8      reserved10[3];
0337     u32     ccr;            /* PSC + 0x30 */
0338     u32     ac97slots;      /* PSC + 0x34 */
0339     u32     ac97cmd;        /* PSC + 0x38 */
0340     u32     ac97data;       /* PSC + 0x3c */
0341     u8      reserved11[4];
0342     u8      ip;         /* PSC + 0x44 */
0343     u8      reserved12[3];
0344     u8      op1;            /* PSC + 0x48 */
0345     u8      reserved13[3];
0346     u8      op0;            /* PSC + 0x4c */
0347     u8      reserved14[3];
0348     u32     sicr;           /* PSC + 0x50 */
0349     u8      reserved15[4];  /* make eq. sizeof(mpc52xx_psc) */
0350 };
0351 
0352 #endif  /* __ASM_MPC52xx_PSC_H__ */
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