include/asm/mpc52xx.h

0001 /*
0002  * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
0003  * May need to be cleaned as the port goes on ...
0004  *
0005  * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
0006  * Copyright (C) 2003 MontaVista, Software, Inc.
0007  *
0008  * This file is licensed under the terms of the GNU General Public License
0009  * version 2. This program is licensed "as is" without any warranty of any
0010  * kind, whether express or implied.
0011  */
0012
0013 #ifndef __ASM_POWERPC_MPC52xx_H__
0014 #define __ASM_POWERPC_MPC52xx_H__
0015
0016 #ifndef __ASSEMBLY__
0017 #include <asm/types.h>
0018 #include <asm/mpc5xxx.h>
0019 #endif /* __ASSEMBLY__ */
0020
0021 #include <linux/suspend.h>
0022
0023 /* Variants of the 5200(B) */
0024 #define MPC5200_SVR     0x80110010
0025 #define MPC5200_SVR_MASK    0xfffffff0
0026 #define MPC5200B_SVR        0x80110020
0027 #define MPC5200B_SVR_MASK   0xfffffff0
0028
0029 /* ======================================================================== */
0030 /* Structures mapping of some unit register set                             */
0031 /* ======================================================================== */
0032
0033 #ifndef __ASSEMBLY__
0034
0035 /* Memory Mapping Control */
0036 struct mpc52xx_mmap_ctl {
0037     u32 mbar;       /* MMAP_CTRL + 0x00 */
0038
0039     u32 cs0_start;      /* MMAP_CTRL + 0x04 */
0040     u32 cs0_stop;       /* MMAP_CTRL + 0x08 */
0041     u32 cs1_start;      /* MMAP_CTRL + 0x0c */
0042     u32 cs1_stop;       /* MMAP_CTRL + 0x10 */
0043     u32 cs2_start;      /* MMAP_CTRL + 0x14 */
0044     u32 cs2_stop;       /* MMAP_CTRL + 0x18 */
0045     u32 cs3_start;      /* MMAP_CTRL + 0x1c */
0046     u32 cs3_stop;       /* MMAP_CTRL + 0x20 */
0047     u32 cs4_start;      /* MMAP_CTRL + 0x24 */
0048     u32 cs4_stop;       /* MMAP_CTRL + 0x28 */
0049     u32 cs5_start;      /* MMAP_CTRL + 0x2c */
0050     u32 cs5_stop;       /* MMAP_CTRL + 0x30 */
0051
0052     u32 sdram0;     /* MMAP_CTRL + 0x34 */
0053     u32 sdram1;     /* MMAP_CTRL + 0X38 */
0054
0055     u32 reserved[4];    /* MMAP_CTRL + 0x3c .. 0x48 */
0056
0057     u32 boot_start;     /* MMAP_CTRL + 0x4c */
0058     u32 boot_stop;      /* MMAP_CTRL + 0x50 */
0059
0060     u32 ipbi_ws_ctrl;   /* MMAP_CTRL + 0x54 */
0061
0062     u32 cs6_start;      /* MMAP_CTRL + 0x58 */
0063     u32 cs6_stop;       /* MMAP_CTRL + 0x5c */
0064     u32 cs7_start;      /* MMAP_CTRL + 0x60 */
0065     u32 cs7_stop;       /* MMAP_CTRL + 0x64 */
0066 };
0067
0068 /* SDRAM control */
0069 struct mpc52xx_sdram {
0070     u32 mode;       /* SDRAM + 0x00 */
0071     u32 ctrl;       /* SDRAM + 0x04 */
0072     u32 config1;        /* SDRAM + 0x08 */
0073     u32 config2;        /* SDRAM + 0x0c */
0074 };
0075
0076 /* SDMA */
0077 struct mpc52xx_sdma {
0078     u32 taskBar;        /* SDMA + 0x00 */
0079     u32 currentPointer; /* SDMA + 0x04 */
0080     u32 endPointer;     /* SDMA + 0x08 */
0081     u32 variablePointer;    /* SDMA + 0x0c */
0082
0083     u8 IntVect1;        /* SDMA + 0x10 */
0084     u8 IntVect2;        /* SDMA + 0x11 */
0085     u16 PtdCntrl;       /* SDMA + 0x12 */
0086
0087     u32 IntPend;        /* SDMA + 0x14 */
0088     u32 IntMask;        /* SDMA + 0x18 */
0089
0090     u16 tcr[16];        /* SDMA + 0x1c .. 0x3a */
0091
0092     u8 ipr[32];     /* SDMA + 0x3c .. 0x5b */
0093
0094     u32 cReqSelect;     /* SDMA + 0x5c */
0095     u32 task_size0;     /* SDMA + 0x60 */
0096     u32 task_size1;     /* SDMA + 0x64 */
0097     u32 MDEDebug;       /* SDMA + 0x68 */
0098     u32 ADSDebug;       /* SDMA + 0x6c */
0099     u32 Value1;     /* SDMA + 0x70 */
0100     u32 Value2;     /* SDMA + 0x74 */
0101     u32 Control;        /* SDMA + 0x78 */
0102     u32 Status;     /* SDMA + 0x7c */
0103     u32 PTDDebug;       /* SDMA + 0x80 */
0104 };
0105
0106 /* GPT */
0107 struct mpc52xx_gpt {
0108     u32 mode;       /* GPTx + 0x00 */
0109     u32 count;      /* GPTx + 0x04 */
0110     u32 pwm;        /* GPTx + 0x08 */
0111     u32 status;     /* GPTx + 0X0c */
0112 };
0113
0114 /* GPIO */
0115 struct mpc52xx_gpio {
0116     u32 port_config;    /* GPIO + 0x00 */
0117     u32 simple_gpioe;   /* GPIO + 0x04 */
0118     u32 simple_ode;     /* GPIO + 0x08 */
0119     u32 simple_ddr;     /* GPIO + 0x0c */
0120     u32 simple_dvo;     /* GPIO + 0x10 */
0121     u32 simple_ival;    /* GPIO + 0x14 */
0122     u8 outo_gpioe;      /* GPIO + 0x18 */
0123     u8 reserved1[3];    /* GPIO + 0x19 */
0124     u8 outo_dvo;        /* GPIO + 0x1c */
0125     u8 reserved2[3];    /* GPIO + 0x1d */
0126     u8 sint_gpioe;      /* GPIO + 0x20 */
0127     u8 reserved3[3];    /* GPIO + 0x21 */
0128     u8 sint_ode;        /* GPIO + 0x24 */
0129     u8 reserved4[3];    /* GPIO + 0x25 */
0130     u8 sint_ddr;        /* GPIO + 0x28 */
0131     u8 reserved5[3];    /* GPIO + 0x29 */
0132     u8 sint_dvo;        /* GPIO + 0x2c */
0133     u8 reserved6[3];    /* GPIO + 0x2d */
0134     u8 sint_inten;      /* GPIO + 0x30 */
0135     u8 reserved7[3];    /* GPIO + 0x31 */
0136     u16 sint_itype;     /* GPIO + 0x34 */
0137     u16 reserved8;      /* GPIO + 0x36 */
0138     u8 gpio_control;    /* GPIO + 0x38 */
0139     u8 reserved9[3];    /* GPIO + 0x39 */
0140     u8 sint_istat;      /* GPIO + 0x3c */
0141     u8 sint_ival;       /* GPIO + 0x3d */
0142     u8 bus_errs;        /* GPIO + 0x3e */
0143     u8 reserved10;      /* GPIO + 0x3f */
0144 };
0145
0146 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
0147 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
0148 #define MPC52xx_GPIO_PCI_DIS            (1<<15)
0149
0150 /* GPIO with WakeUp*/
0151 struct mpc52xx_gpio_wkup {
0152     u8 wkup_gpioe;      /* GPIO_WKUP + 0x00 */
0153     u8 reserved1[3];    /* GPIO_WKUP + 0x03 */
0154     u8 wkup_ode;        /* GPIO_WKUP + 0x04 */
0155     u8 reserved2[3];    /* GPIO_WKUP + 0x05 */
0156     u8 wkup_ddr;        /* GPIO_WKUP + 0x08 */
0157     u8 reserved3[3];    /* GPIO_WKUP + 0x09 */
0158     u8 wkup_dvo;        /* GPIO_WKUP + 0x0C */
0159     u8 reserved4[3];    /* GPIO_WKUP + 0x0D */
0160     u8 wkup_inten;      /* GPIO_WKUP + 0x10 */
0161     u8 reserved5[3];    /* GPIO_WKUP + 0x11 */
0162     u8 wkup_iinten;     /* GPIO_WKUP + 0x14 */
0163     u8 reserved6[3];    /* GPIO_WKUP + 0x15 */
0164     u16 wkup_itype;     /* GPIO_WKUP + 0x18 */
0165     u8 reserved7[2];    /* GPIO_WKUP + 0x1A */
0166     u8 wkup_maste;      /* GPIO_WKUP + 0x1C */
0167     u8 reserved8[3];    /* GPIO_WKUP + 0x1D */
0168     u8 wkup_ival;       /* GPIO_WKUP + 0x20 */
0169     u8 reserved9[3];    /* GPIO_WKUP + 0x21 */
0170     u8 wkup_istat;      /* GPIO_WKUP + 0x24 */
0171     u8 reserved10[3];   /* GPIO_WKUP + 0x25 */
0172 };
0173
0174 /* XLB Bus control */
0175 struct mpc52xx_xlb {
0176     u8 reserved[0x40];
0177     u32 config;     /* XLB + 0x40 */
0178     u32 version;        /* XLB + 0x44 */
0179     u32 status;     /* XLB + 0x48 */
0180     u32 int_enable;     /* XLB + 0x4c */
0181     u32 addr_capture;   /* XLB + 0x50 */
0182     u32 bus_sig_capture;    /* XLB + 0x54 */
0183     u32 addr_timeout;   /* XLB + 0x58 */
0184     u32 data_timeout;   /* XLB + 0x5c */
0185     u32 bus_act_timeout;    /* XLB + 0x60 */
0186     u32 master_pri_enable;  /* XLB + 0x64 */
0187     u32 master_priority;    /* XLB + 0x68 */
0188     u32 base_address;   /* XLB + 0x6c */
0189     u32 snoop_window;   /* XLB + 0x70 */
0190 };
0191
0192 #define MPC52xx_XLB_CFG_PLDIS       (1 << 31)
0193 #define MPC52xx_XLB_CFG_SNOOP       (1 << 15)
0194
0195 /* Clock Distribution control */
0196 struct mpc52xx_cdm {
0197     u32 jtag_id;        /* CDM + 0x00  reg0 read only */
0198     u32 rstcfg;     /* CDM + 0x04  reg1 read only */
0199     u32 breadcrumb;     /* CDM + 0x08  reg2 */
0200
0201     u8 mem_clk_sel;     /* CDM + 0x0c  reg3 byte0 */
0202     u8 xlb_clk_sel;     /* CDM + 0x0d  reg3 byte1 read only */
0203     u8 ipb_clk_sel;     /* CDM + 0x0e  reg3 byte2 */
0204     u8 pci_clk_sel;     /* CDM + 0x0f  reg3 byte3 */
0205
0206     u8 ext_48mhz_en;    /* CDM + 0x10  reg4 byte0 */
0207     u8 fd_enable;       /* CDM + 0x11  reg4 byte1 */
0208     u16 fd_counters;    /* CDM + 0x12  reg4 byte2,3 */
0209
0210     u32 clk_enables;    /* CDM + 0x14  reg5 */
0211
0212     u8 osc_disable;     /* CDM + 0x18  reg6 byte0 */
0213     u8 reserved0[3];    /* CDM + 0x19  reg6 byte1,2,3 */
0214
0215     u8 ccs_sleep_enable;    /* CDM + 0x1c  reg7 byte0 */
0216     u8 osc_sleep_enable;    /* CDM + 0x1d  reg7 byte1 */
0217     u8 reserved1;       /* CDM + 0x1e  reg7 byte2 */
0218     u8 ccs_qreq_test;   /* CDM + 0x1f  reg7 byte3 */
0219
0220     u8 soft_reset;      /* CDM + 0x20  u8 byte0 */
0221     u8 no_ckstp;        /* CDM + 0x21  u8 byte0 */
0222     u8 reserved2[2];    /* CDM + 0x22  u8 byte1,2,3 */
0223
0224     u8 pll_lock;        /* CDM + 0x24  reg9 byte0 */
0225     u8 pll_looselock;   /* CDM + 0x25  reg9 byte1 */
0226     u8 pll_sm_lockwin;  /* CDM + 0x26  reg9 byte2 */
0227     u8 reserved3;       /* CDM + 0x27  reg9 byte3 */
0228
0229     u16 reserved4;      /* CDM + 0x28  reg10 byte0,1 */
0230     u16 mclken_div_psc1;    /* CDM + 0x2a  reg10 byte2,3 */
0231
0232     u16 reserved5;      /* CDM + 0x2c  reg11 byte0,1 */
0233     u16 mclken_div_psc2;    /* CDM + 0x2e  reg11 byte2,3 */
0234
0235     u16 reserved6;      /* CDM + 0x30  reg12 byte0,1 */
0236     u16 mclken_div_psc3;    /* CDM + 0x32  reg12 byte2,3 */
0237
0238     u16 reserved7;      /* CDM + 0x34  reg13 byte0,1 */
0239     u16 mclken_div_psc6;    /* CDM + 0x36  reg13 byte2,3 */
0240 };
0241
0242 /* Interrupt controller Register set */
0243 struct mpc52xx_intr {
0244     u32 per_mask;       /* INTR + 0x00 */
0245     u32 per_pri1;       /* INTR + 0x04 */
0246     u32 per_pri2;       /* INTR + 0x08 */
0247     u32 per_pri3;       /* INTR + 0x0c */
0248     u32 ctrl;       /* INTR + 0x10 */
0249     u32 main_mask;      /* INTR + 0x14 */
0250     u32 main_pri1;      /* INTR + 0x18 */
0251     u32 main_pri2;      /* INTR + 0x1c */
0252     u32 reserved1;      /* INTR + 0x20 */
0253     u32 enc_status;     /* INTR + 0x24 */
0254     u32 crit_status;    /* INTR + 0x28 */
0255     u32 main_status;    /* INTR + 0x2c */
0256     u32 per_status;     /* INTR + 0x30 */
0257     u32 reserved2;      /* INTR + 0x34 */
0258     u32 per_error;      /* INTR + 0x38 */
0259 };
0260
0261 #endif /* __ASSEMBLY__ */
0262
0263
0264 /* ========================================================================= */
0265 /* Prototypes for MPC52xx sysdev                                             */
0266 /* ========================================================================= */
0267
0268 #ifndef __ASSEMBLY__
0269
0270 struct device_node;
0271
0272 /* mpc52xx_common.c */
0273 extern void mpc5200_setup_xlb_arbiter(void);
0274 extern void mpc52xx_declare_of_platform_devices(void);
0275 extern int mpc5200_psc_ac97_gpio_reset(int psc_number);
0276 extern void mpc52xx_map_common_devices(void);
0277 extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
0278 extern void __noreturn mpc52xx_restart(char *cmd);
0279
0280 /* mpc52xx_gpt.c */
0281 struct mpc52xx_gpt_priv;
0282 extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
0283 extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
0284                             int continuous);
0285 extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
0286 extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
0287
0288 /* mpc52xx_lpbfifo.c */
0289 #define MPC52XX_LPBFIFO_FLAG_READ       (0)
0290 #define MPC52XX_LPBFIFO_FLAG_WRITE      (1<<0)
0291 #define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT   (1<<1)
0292 #define MPC52XX_LPBFIFO_FLAG_NO_DMA     (1<<2)
0293 #define MPC52XX_LPBFIFO_FLAG_POLL_DMA       (1<<3)
0294
0295 struct mpc52xx_lpbfifo_request {
0296     struct list_head list;
0297
0298     /* localplus bus address */
0299     unsigned int cs;
0300     size_t offset;
0301
0302     /* Memory address */
0303     void *data;
0304     phys_addr_t data_phys;
0305
0306     /* Details of transfer */
0307     size_t size;
0308     size_t pos; /* current position of transfer */
0309     int flags;
0310     int defer_xfer_start;
0311
0312     /* What to do when finished */
0313     void (*callback)(struct mpc52xx_lpbfifo_request *);
0314
0315     void *priv;     /* Driver private data */
0316
0317     /* statistics */
0318     int irq_count;
0319     int irq_ticks;
0320     u8 last_byte;
0321     int buffer_not_done_cnt;
0322 };
0323
0324 extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
0325 extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
0326 extern void mpc52xx_lpbfifo_poll(void);
0327 extern int mpc52xx_lpbfifo_start_xfer(struct mpc52xx_lpbfifo_request *req);
0328
0329 /* mpc52xx_pic.c */
0330 extern void mpc52xx_init_irq(void);
0331 extern unsigned int mpc52xx_get_irq(void);
0332
0333 /* mpc52xx_pci.c */
0334 #ifdef CONFIG_PCI
0335 extern int __init mpc52xx_add_bridge(struct device_node *node);
0336 extern void __init mpc52xx_setup_pci(void);
0337 #else
0338 static inline void mpc52xx_setup_pci(void) { }
0339 #endif
0340
0341 #endif /* __ASSEMBLY__ */
0342
0343 #ifdef CONFIG_PM
0344 struct mpc52xx_suspend {
0345     void (*board_suspend_prepare)(void __iomem *mbar);
0346     void (*board_resume_finish)(void __iomem *mbar);
0347 };
0348
0349 extern struct mpc52xx_suspend mpc52xx_suspend;
0350 extern int __init mpc52xx_pm_init(void);
0351 extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
0352
0353 /* lite5200 calls mpc5200 suspend functions, so here they are */
0354 extern int mpc52xx_pm_prepare(void);
0355 extern int mpc52xx_pm_enter(suspend_state_t);
0356 extern void mpc52xx_pm_finish(void);
0357 extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
0358
0359 #ifdef CONFIG_PPC_LITE5200
0360 int __init lite5200_pm_init(void);
0361 #endif
0362 #endif /* CONFIG_PM */
0363
0364 #endif /* __ASM_POWERPC_MPC52xx_H__ */
0365