include/asm/mpc5121.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * MPC5121 Prototypes and definitions
0004  */
0005
0006 #ifndef __ASM_POWERPC_MPC5121_H__
0007 #define __ASM_POWERPC_MPC5121_H__
0008
0009 /* MPC512x Reset module registers */
0010 struct mpc512x_reset_module {
0011     u32 rcwlr;  /* Reset Configuration Word Low Register */
0012     u32 rcwhr;  /* Reset Configuration Word High Register */
0013     u32 reserved1;
0014     u32 reserved2;
0015     u32 rsr;    /* Reset Status Register */
0016     u32 rmr;    /* Reset Mode Register */
0017     u32 rpr;    /* Reset Protection Register */
0018     u32 rcr;    /* Reset Control Register */
0019     u32 rcer;   /* Reset Control Enable Register */
0020 };
0021
0022 /*
0023  * Clock Control Module
0024  */
0025 struct mpc512x_ccm {
0026     u32 spmr;   /* System PLL Mode Register */
0027     u32 sccr1;  /* System Clock Control Register 1 */
0028     u32 sccr2;  /* System Clock Control Register 2 */
0029     u32 scfr1;  /* System Clock Frequency Register 1 */
0030     u32 scfr2;  /* System Clock Frequency Register 2 */
0031     u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
0032     u32 bcr;    /* Bread Crumb Register */
0033     u32 psc_ccr[12];    /* PSC Clock Control Registers */
0034     u32 spccr;  /* SPDIF Clock Control Register */
0035     u32 cccr;   /* CFM Clock Control Register */
0036     u32 dccr;   /* DIU Clock Control Register */
0037     u32 mscan_ccr[4];   /* MSCAN Clock Control Registers */
0038     u32 out_ccr[4]; /* OUT CLK Configure Registers */
0039     u32 rsv0[2];    /* Reserved */
0040     u32 scfr3;      /* System Clock Frequency Register 3 */
0041     u32 rsv1[3];    /* Reserved */
0042     u32 spll_lock_cnt;  /* System PLL Lock Counter */
0043     u8  res[0x6c];  /* Reserved */
0044 };
0045
0046 /*
0047  * LPC Module
0048  */
0049 struct mpc512x_lpc {
0050     u32 cs_cfg[8];  /* CS config */
0051     u32 cs_ctrl;    /* CS Control Register */
0052     u32 cs_status;  /* CS Status Register */
0053     u32 burst_ctrl; /* CS Burst Control Register */
0054     u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
0055     u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
0056     u32 alt;        /* Address Latch Timing Register */
0057 };
0058
0059 int mpc512x_cs_config(unsigned int cs, u32 val);
0060
0061 /*
0062  * SCLPC Module (LPB FIFO)
0063  */
0064 struct mpc512x_lpbfifo {
0065     u32 pkt_size;   /* SCLPC Packet Size Register */
0066     u32 start_addr; /* SCLPC Start Address Register */
0067     u32 ctrl;       /* SCLPC Control Register */
0068     u32 enable;     /* SCLPC Enable Register */
0069     u32 reserved1;
0070     u32 status;     /* SCLPC Status Register */
0071     u32 bytes_done; /* SCLPC Bytes Done Register */
0072     u32 emb_sc;     /* EMB Share Counter Register */
0073     u32 emb_pc;     /* EMB Pause Control Register */
0074     u32 reserved2[7];
0075     u32 data_word;  /* LPC RX/TX FIFO Data Word Register */
0076     u32 fifo_status;    /* LPC RX/TX FIFO Status Register */
0077     u32 fifo_ctrl;  /* LPC RX/TX FIFO Control Register */
0078     u32 fifo_alarm; /* LPC RX/TX FIFO Alarm Register */
0079 };
0080
0081 #define MPC512X_SCLPC_START     (1 << 31)
0082 #define MPC512X_SCLPC_CS(x)     (((x) & 0x7) << 24)
0083 #define MPC512X_SCLPC_FLUSH     (1 << 17)
0084 #define MPC512X_SCLPC_READ      (1 << 16)
0085 #define MPC512X_SCLPC_DAI       (1 << 8)
0086 #define MPC512X_SCLPC_BPT(x)        ((x) & 0x3f)
0087 #define MPC512X_SCLPC_RESET     (1 << 24)
0088 #define MPC512X_SCLPC_FIFO_RESET    (1 << 16)
0089 #define MPC512X_SCLPC_ABORT_INT_ENABLE  (1 << 9)
0090 #define MPC512X_SCLPC_NORM_INT_ENABLE   (1 << 8)
0091 #define MPC512X_SCLPC_ENABLE        (1 << 0)
0092 #define MPC512X_SCLPC_SUCCESS       (1 << 24)
0093 #define MPC512X_SCLPC_FIFO_CTRL(x)  (((x) & 0x7) << 24)
0094 #define MPC512X_SCLPC_FIFO_ALARM(x) ((x) & 0x3ff)
0095
0096 enum lpb_dev_portsize {
0097     LPB_DEV_PORTSIZE_UNDEFINED = 0,
0098     LPB_DEV_PORTSIZE_1_BYTE = 1,
0099     LPB_DEV_PORTSIZE_2_BYTES = 2,
0100     LPB_DEV_PORTSIZE_4_BYTES = 4,
0101     LPB_DEV_PORTSIZE_8_BYTES = 8
0102 };
0103
0104 enum mpc512x_lpbfifo_req_dir {
0105     MPC512X_LPBFIFO_REQ_DIR_READ,
0106     MPC512X_LPBFIFO_REQ_DIR_WRITE
0107 };
0108
0109 struct mpc512x_lpbfifo_request {
0110     phys_addr_t dev_phys_addr; /* physical address of some device on LPB */
0111     void *ram_virt_addr; /* virtual address of some region in RAM */
0112     u32 size;
0113     enum lpb_dev_portsize portsize;
0114     enum mpc512x_lpbfifo_req_dir dir;
0115     void (*callback)(struct mpc512x_lpbfifo_request *);
0116 };
0117
0118 int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);
0119
0120 #endif /* __ASM_POWERPC_MPC5121_H__ */