include/asm/keylargo.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_KEYLARGO_H
0003 #define _ASM_POWERPC_KEYLARGO_H
0004 #ifdef __KERNEL__
0005 /*
0006  * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
0007  *
0008  */
0009
0010 /* "Pangea" chipset has keylargo device-id 0x25 while core99
0011  * has device-id 0x22. The rev. of the pangea one is 0, so we
0012  * fake an artificial rev. in keylargo_rev by oring 0x100
0013  */
0014 #define KL_PANGEA_REV       0x100
0015
0016 /* offset from base for feature control registers */
0017 #define KEYLARGO_MBCR       0x34    /* KL Only, Media bay control/status */
0018 #define KEYLARGO_FCR0       0x38
0019 #define KEYLARGO_FCR1       0x3c
0020 #define KEYLARGO_FCR2       0x40
0021 #define KEYLARGO_FCR3       0x44
0022 #define KEYLARGO_FCR4       0x48
0023 #define KEYLARGO_FCR5       0x4c    /* Pangea only */
0024
0025 /* K2 additional FCRs */
0026 #define K2_FCR6         0x34
0027 #define K2_FCR7         0x30
0028 #define K2_FCR8         0x2c
0029 #define K2_FCR9         0x28
0030 #define K2_FCR10        0x24
0031
0032 /* GPIO registers */
0033 #define KEYLARGO_GPIO_LEVELS0       0x50
0034 #define KEYLARGO_GPIO_LEVELS1       0x54
0035 #define KEYLARGO_GPIO_EXTINT_0      0x58
0036 #define KEYLARGO_GPIO_EXTINT_CNT    18
0037 #define KEYLARGO_GPIO_0         0x6A
0038 #define KEYLARGO_GPIO_CNT       17
0039 #define KEYLARGO_GPIO_EXTINT_DUAL_EDGE  0x80
0040 #define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
0041 #define KEYLARGO_GPIO_OUTOUT_DATA   0x01
0042 #define KEYLARGO_GPIO_INPUT_DATA    0x02
0043
0044 /* K2 does only extint GPIOs and does 51 of them */
0045 #define K2_GPIO_EXTINT_0        0x58
0046 #define K2_GPIO_EXTINT_CNT      51
0047
0048 /* Specific GPIO regs */
0049
0050 #define KL_GPIO_MODEM_RESET     (KEYLARGO_GPIO_0+0x03)
0051 #define KL_GPIO_MODEM_POWER     (KEYLARGO_GPIO_0+0x02) /* Pangea */
0052
0053 #define KL_GPIO_SOUND_POWER     (KEYLARGO_GPIO_0+0x05)
0054
0055 /* Hrm... this one is only to be used on Pismo. It seems to also
0056  * control the timebase enable on other machines. Still to be
0057  * experimented... --BenH.
0058  */
0059 #define KL_GPIO_FW_CABLE_POWER      (KEYLARGO_GPIO_0+0x09)
0060 #define KL_GPIO_TB_ENABLE       (KEYLARGO_GPIO_0+0x09)
0061
0062 #define KL_GPIO_ETH_PHY_RESET       (KEYLARGO_GPIO_0+0x10)
0063
0064 #define KL_GPIO_EXTINT_CPU1     (KEYLARGO_GPIO_0+0x0a)
0065 #define KL_GPIO_EXTINT_CPU1_ASSERT  0x04
0066 #define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
0067
0068 #define KL_GPIO_RESET_CPU0      (KEYLARGO_GPIO_EXTINT_0+0x03)
0069 #define KL_GPIO_RESET_CPU1      (KEYLARGO_GPIO_EXTINT_0+0x04)
0070 #define KL_GPIO_RESET_CPU2      (KEYLARGO_GPIO_EXTINT_0+0x0f)
0071 #define KL_GPIO_RESET_CPU3      (KEYLARGO_GPIO_EXTINT_0+0x10)
0072
0073 #define KL_GPIO_PMU_MESSAGE_IRQ     (KEYLARGO_GPIO_EXTINT_0+0x09)
0074 #define KL_GPIO_PMU_MESSAGE_BIT     KEYLARGO_GPIO_INPUT_DATA
0075
0076 #define KL_GPIO_MEDIABAY_IRQ        (KEYLARGO_GPIO_EXTINT_0+0x0e)
0077
0078 #define KL_GPIO_AIRPORT_0       (KEYLARGO_GPIO_EXTINT_0+0x0a)
0079 #define KL_GPIO_AIRPORT_1       (KEYLARGO_GPIO_EXTINT_0+0x0d)
0080 #define KL_GPIO_AIRPORT_2       (KEYLARGO_GPIO_0+0x0d)
0081 #define KL_GPIO_AIRPORT_3       (KEYLARGO_GPIO_0+0x0e)
0082 #define KL_GPIO_AIRPORT_4       (KEYLARGO_GPIO_0+0x0f)
0083
0084 /*
0085  * Bits in feature control register. Those bits different for K2 are
0086  * listed separately
0087  */
0088 #define KL_MBCR_MB0_PCI_ENABLE      0x00000800  /* exist ? */
0089 #define KL_MBCR_MB0_IDE_ENABLE      0x00001000
0090 #define KL_MBCR_MB0_FLOPPY_ENABLE   0x00002000  /* exist ? */
0091 #define KL_MBCR_MB0_SOUND_ENABLE    0x00004000  /* hrm... */
0092 #define KL_MBCR_MB0_DEV_MASK        0x00007800
0093 #define KL_MBCR_MB0_DEV_POWER       0x00000400
0094 #define KL_MBCR_MB0_DEV_RESET       0x00000200
0095 #define KL_MBCR_MB0_ENABLE      0x00000100
0096 #define KL_MBCR_MB1_PCI_ENABLE      0x08000000  /* exist ? */
0097 #define KL_MBCR_MB1_IDE_ENABLE      0x10000000
0098 #define KL_MBCR_MB1_FLOPPY_ENABLE   0x20000000  /* exist ? */
0099 #define KL_MBCR_MB1_SOUND_ENABLE    0x40000000  /* hrm... */
0100 #define KL_MBCR_MB1_DEV_MASK        0x78000000
0101 #define KL_MBCR_MB1_DEV_POWER       0x04000000
0102 #define KL_MBCR_MB1_DEV_RESET       0x02000000
0103 #define KL_MBCR_MB1_ENABLE      0x01000000
0104
0105 #define KL0_SCC_B_INTF_ENABLE       0x00000001  /* (KL Only) */
0106 #define KL0_SCC_A_INTF_ENABLE       0x00000002
0107 #define KL0_SCC_SLOWPCLK        0x00000004
0108 #define KL0_SCC_RESET           0x00000008
0109 #define KL0_SCCA_ENABLE         0x00000010
0110 #define KL0_SCCB_ENABLE         0x00000020
0111 #define KL0_SCC_CELL_ENABLE     0x00000040
0112 #define KL0_IRDA_HIGH_BAND      0x00000100  /* (KL Only) */
0113 #define KL0_IRDA_SOURCE2_SEL        0x00000200  /* (KL Only) */
0114 #define KL0_IRDA_SOURCE1_SEL        0x00000400  /* (KL Only) */
0115 #define KL0_PG_USB0_PMI_ENABLE      0x00000400  /* (Pangea/Intrepid Only) */
0116 #define KL0_IRDA_RESET          0x00000800  /* (KL Only) */
0117 #define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800  /* (Pangea/Intrepid Only) */
0118 #define KL0_IRDA_DEFAULT1       0x00001000  /* (KL Only) */
0119 #define KL0_PG_USB0_REF_SUSPEND     0x00001000  /* (Pangea/Intrepid Only) */
0120 #define KL0_IRDA_DEFAULT0       0x00002000  /* (KL Only) */
0121 #define KL0_PG_USB0_PAD_SUSPEND     0x00002000  /* (Pangea/Intrepid Only) */
0122 #define KL0_IRDA_FAST_CONNECT       0x00004000  /* (KL Only) */
0123 #define KL0_PG_USB1_PMI_ENABLE      0x00004000  /* (Pangea/Intrepid Only) */
0124 #define KL0_IRDA_ENABLE         0x00008000  /* (KL Only) */
0125 #define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000  /* (Pangea/Intrepid Only) */
0126 #define KL0_IRDA_CLK32_ENABLE       0x00010000  /* (KL Only) */
0127 #define KL0_PG_USB1_REF_SUSPEND     0x00010000  /* (Pangea/Intrepid Only) */
0128 #define KL0_IRDA_CLK19_ENABLE       0x00020000  /* (KL Only) */
0129 #define KL0_PG_USB1_PAD_SUSPEND     0x00020000  /* (Pangea/Intrepid Only) */
0130 #define KL0_USB0_PAD_SUSPEND0       0x00040000
0131 #define KL0_USB0_PAD_SUSPEND1       0x00080000
0132 #define KL0_USB0_CELL_ENABLE        0x00100000
0133 #define KL0_USB1_PAD_SUSPEND0       0x00400000
0134 #define KL0_USB1_PAD_SUSPEND1       0x00800000
0135 #define KL0_USB1_CELL_ENABLE        0x01000000
0136 #define KL0_USB_REF_SUSPEND     0x10000000  /* (KL Only) */
0137
0138 #define KL0_SERIAL_ENABLE       (KL0_SCC_B_INTF_ENABLE | \
0139                     KL0_SCC_SLOWPCLK | \
0140                     KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
0141
0142 #define KL1_USB2_PMI_ENABLE     0x00000001  /* Intrepid only */
0143 #define KL1_AUDIO_SEL_22MCLK        0x00000002  /* KL/Pangea only */
0144 #define KL1_USB2_REF_SUSPEND_SEL    0x00000002  /* Intrepid only */
0145 #define KL1_USB2_REF_SUSPEND        0x00000004  /* Intrepid only */
0146 #define KL1_AUDIO_CLK_ENABLE_BIT    0x00000008  /* KL/Pangea only */
0147 #define KL1_USB2_PAD_SUSPEND_SEL    0x00000008  /* Intrepid only */
0148 #define KL1_USB2_PAD_SUSPEND0       0x00000010  /* Intrepid only */
0149 #define KL1_AUDIO_CLK_OUT_ENABLE    0x00000020  /* KL/Pangea only */
0150 #define KL1_USB2_PAD_SUSPEND1       0x00000020  /* Intrepid only */
0151 #define KL1_AUDIO_CELL_ENABLE       0x00000040  /* KL/Pangea only */
0152 #define KL1_USB2_CELL_ENABLE        0x00000040  /* Intrepid only */
0153 #define KL1_AUDIO_CHOOSE        0x00000080  /* KL/Pangea only */
0154 #define KL1_I2S0_CHOOSE         0x00000200  /* KL Only */
0155 #define KL1_I2S0_CELL_ENABLE        0x00000400
0156 #define KL1_I2S0_CLK_ENABLE_BIT     0x00001000
0157 #define KL1_I2S0_ENABLE         0x00002000
0158 #define KL1_I2S1_CELL_ENABLE        0x00020000
0159 #define KL1_I2S1_CLK_ENABLE_BIT     0x00080000
0160 #define KL1_I2S1_ENABLE         0x00100000
0161 #define KL1_EIDE0_ENABLE        0x00800000  /* KL/Intrepid Only */
0162 #define KL1_EIDE0_RESET_N       0x01000000  /* KL/Intrepid Only */
0163 #define KL1_EIDE1_ENABLE        0x04000000  /* KL Only */
0164 #define KL1_EIDE1_RESET_N       0x08000000  /* KL Only */
0165 #define KL1_UIDE_ENABLE         0x20000000  /* KL/Pangea Only */
0166 #define KL1_UIDE_RESET_N        0x40000000  /* KL/Pangea Only */
0167
0168 #define KL2_IOBUS_ENABLE        0x00000002
0169 #define KL2_SLEEP_STATE_BIT     0x00000100  /* KL Only */
0170 #define KL2_PG_STOP_ALL_CLOCKS      0x00000100  /* Pangea Only */
0171 #define KL2_MPIC_ENABLE         0x00020000
0172 #define KL2_CARDSLOT_RESET      0x00040000  /* Pangea/Intrepid Only */
0173 #define KL2_ALT_DATA_OUT        0x02000000  /* KL Only ??? */
0174 #define KL2_MEM_IS_BIG          0x04000000
0175 #define KL2_CARDSEL_16          0x08000000
0176
0177 #define KL3_SHUTDOWN_PLL_TOTAL      0x00000001  /* KL/Pangea only */
0178 #define KL3_SHUTDOWN_PLLKW6     0x00000002  /* KL/Pangea only */
0179 #define KL3_IT_SHUTDOWN_PLL3        0x00000002  /* Intrepid only */
0180 #define KL3_SHUTDOWN_PLLKW4     0x00000004  /* KL/Pangea only */
0181 #define KL3_IT_SHUTDOWN_PLL2        0x00000004  /* Intrepid only */
0182 #define KL3_SHUTDOWN_PLLKW35        0x00000008  /* KL/Pangea only */
0183 #define KL3_IT_SHUTDOWN_PLL1        0x00000008  /* Intrepid only */
0184 #define KL3_SHUTDOWN_PLLKW12        0x00000010  /* KL Only */
0185 #define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010  /* Intrepid only */
0186 #define KL3_PLL_RESET           0x00000020  /* KL/Pangea only */
0187 #define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020  /* Intrepid only */
0188 #define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010  /* Intrepid only */
0189 #define KL3_SHUTDOWN_PLL2X      0x00000080  /* KL Only */
0190 #define KL3_CLK66_ENABLE        0x00000100  /* KL Only */
0191 #define KL3_CLK49_ENABLE        0x00000200
0192 #define KL3_CLK45_ENABLE        0x00000400
0193 #define KL3_CLK31_ENABLE        0x00000800  /* KL/Pangea only */
0194 #define KL3_TIMER_CLK18_ENABLE      0x00001000
0195 #define KL3_I2S1_CLK18_ENABLE       0x00002000
0196 #define KL3_I2S0_CLK18_ENABLE       0x00004000
0197 #define KL3_VIA_CLK16_ENABLE        0x00008000  /* KL/Pangea only */
0198 #define KL3_IT_VIA_CLK32_ENABLE     0x00008000  /* Intrepid only */
0199 #define KL3_STOPPING33_ENABLED      0x00080000  /* KL Only */
0200 #define KL3_PG_PLL_ENABLE_TEST      0x00080000  /* Pangea Only */
0201
0202 /* Intrepid USB bus 2, port 0,1 */
0203 #define KL3_IT_PORT_WAKEUP_ENABLE(p)        (0x00080000 << ((p)<<3))
0204 #define KL3_IT_PORT_RESUME_WAKE_EN(p)       (0x00040000 << ((p)<<3))
0205 #define KL3_IT_PORT_CONNECT_WAKE_EN(p)      (0x00020000 << ((p)<<3))
0206 #define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)   (0x00010000 << ((p)<<3))
0207 #define KL3_IT_PORT_RESUME_STAT(p)      (0x00300000 << ((p)<<3))
0208 #define KL3_IT_PORT_CONNECT_STAT(p)     (0x00200000 << ((p)<<3))
0209 #define KL3_IT_PORT_DISCONNECT_STAT(p)      (0x00100000 << ((p)<<3))
0210
0211 /* Port 0,1 : bus 0, port 2,3 : bus 1 */
0212 #define KL4_PORT_WAKEUP_ENABLE(p)   (0x00000008 << ((p)<<3))
0213 #define KL4_PORT_RESUME_WAKE_EN(p)  (0x00000004 << ((p)<<3))
0214 #define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
0215 #define KL4_PORT_DISCONNECT_WAKE_EN(p)  (0x00000001 << ((p)<<3))
0216 #define KL4_PORT_RESUME_STAT(p)     (0x00000040 << ((p)<<3))
0217 #define KL4_PORT_CONNECT_STAT(p)    (0x00000020 << ((p)<<3))
0218 #define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
0219
0220 /* Pangea and Intrepid only */
0221 #define KL5_VIA_USE_CLK31       0000000001  /* Pangea Only */
0222 #define KL5_SCC_USE_CLK31       0x00000002  /* Pangea Only */
0223 #define KL5_PWM_CLK32_EN        0x00000004
0224 #define KL5_CLK3_68_EN          0x00000010
0225 #define KL5_CLK32_EN            0x00000020
0226
0227
0228 /* K2 definitions */
0229 #define K2_FCR0_USB0_SWRESET        0x00200000
0230 #define K2_FCR0_USB1_SWRESET        0x02000000
0231 #define K2_FCR0_RING_PME_DISABLE    0x08000000
0232
0233 #define K2_FCR1_PCI1_BUS_RESET_N    0x00000010
0234 #define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
0235 #define K2_FCR1_I2S0_CELL_ENABLE    0x00000400
0236 #define K2_FCR1_I2S0_RESET      0x00000800
0237 #define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
0238 #define K2_FCR1_I2S0_ENABLE         0x00002000
0239 #define K2_FCR1_PCI1_CLK_ENABLE     0x00004000
0240 #define K2_FCR1_FW_CLK_ENABLE       0x00008000
0241 #define K2_FCR1_FW_RESET_N      0x00010000
0242 #define K2_FCR1_I2S1_CELL_ENABLE    0x00020000
0243 #define K2_FCR1_I2S1_CLK_ENABLE_BIT 0x00080000
0244 #define K2_FCR1_I2S1_ENABLE     0x00100000
0245 #define K2_FCR1_GMAC_CLK_ENABLE     0x00400000
0246 #define K2_FCR1_GMAC_POWER_DOWN     0x00800000
0247 #define K2_FCR1_GMAC_RESET_N        0x01000000
0248 #define K2_FCR1_SATA_CLK_ENABLE     0x02000000
0249 #define K2_FCR1_SATA_POWER_DOWN     0x04000000
0250 #define K2_FCR1_SATA_RESET_N        0x08000000
0251 #define K2_FCR1_UATA_CLK_ENABLE     0x10000000
0252 #define K2_FCR1_UATA_RESET_N        0x40000000
0253 #define K2_FCR1_UATA_CHOOSE_CLK66   0x80000000
0254
0255 /* Shasta definitions */
0256 #define SH_FCR1_I2S2_CELL_ENABLE    0x00000010
0257 #define SH_FCR1_I2S2_CLK_ENABLE_BIT 0x00000040
0258 #define SH_FCR1_I2S2_ENABLE     0x00000080
0259 #define SH_FCR3_I2S2_CLK18_ENABLE   0x00008000
0260
0261 #endif /* __KERNEL__ */
0262 #endif /* _ASM_POWERPC_KEYLARGO_H */