include/asm/ipic.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * IPIC external definitions and structure.
0004  *
0005  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
0006  *
0007  * Copyright 2005 Freescale Semiconductor, Inc
0008  */
0009 #ifdef __KERNEL__
0010 #ifndef __ASM_IPIC_H__
0011 #define __ASM_IPIC_H__
0012
0013 #include <linux/irq.h>
0014
0015 /* Flags when we init the IPIC */
0016 #define IPIC_SPREADMODE_GRP_A   0x00000001
0017 #define IPIC_SPREADMODE_GRP_B   0x00000002
0018 #define IPIC_SPREADMODE_GRP_C   0x00000004
0019 #define IPIC_SPREADMODE_GRP_D   0x00000008
0020 #define IPIC_SPREADMODE_MIX_A   0x00000010
0021 #define IPIC_SPREADMODE_MIX_B   0x00000020
0022 #define IPIC_DISABLE_MCP_OUT    0x00000040
0023 #define IPIC_IRQ0_MCP       0x00000080
0024
0025 /* IPIC registers offsets */
0026 #define IPIC_SICFR  0x00    /* System Global Interrupt Configuration Register */
0027 #define IPIC_SIVCR  0x04    /* System Global Interrupt Vector Register */
0028 #define IPIC_SIPNR_H    0x08    /* System Internal Interrupt Pending Register (HIGH) */
0029 #define IPIC_SIPNR_L    0x0C    /* System Internal Interrupt Pending Register (LOW) */
0030 #define IPIC_SIPRR_A    0x10    /* System Internal Interrupt group A Priority Register */
0031 #define IPIC_SIPRR_B    0x14    /* System Internal Interrupt group B Priority Register */
0032 #define IPIC_SIPRR_C    0x18    /* System Internal Interrupt group C Priority Register */
0033 #define IPIC_SIPRR_D    0x1C    /* System Internal Interrupt group D Priority Register */
0034 #define IPIC_SIMSR_H    0x20    /* System Internal Interrupt Mask Register (HIGH) */
0035 #define IPIC_SIMSR_L    0x24    /* System Internal Interrupt Mask Register (LOW) */
0036 #define IPIC_SICNR  0x28    /* System Internal Interrupt Control Register */
0037 #define IPIC_SEPNR  0x2C    /* System External Interrupt Pending Register */
0038 #define IPIC_SMPRR_A    0x30    /* System Mixed Interrupt group A Priority Register */
0039 #define IPIC_SMPRR_B    0x34    /* System Mixed Interrupt group B Priority Register */
0040 #define IPIC_SEMSR  0x38    /* System External Interrupt Mask Register */
0041 #define IPIC_SECNR  0x3C    /* System External Interrupt Control Register */
0042 #define IPIC_SERSR  0x40    /* System Error Status Register */
0043 #define IPIC_SERMR  0x44    /* System Error Mask Register */
0044 #define IPIC_SERCR  0x48    /* System Error Control Register */
0045 #define IPIC_SIFCR_H    0x50    /* System Internal Interrupt Force Register (HIGH) */
0046 #define IPIC_SIFCR_L    0x54    /* System Internal Interrupt Force Register (LOW) */
0047 #define IPIC_SEFCR  0x58    /* System External Interrupt Force Register */
0048 #define IPIC_SERFR  0x5C    /* System Error Force Register */
0049 #define IPIC_SCVCR  0x60    /* System Critical Interrupt Vector Register */
0050 #define IPIC_SMVCR  0x64    /* System Management Interrupt Vector Register */
0051
0052 enum ipic_prio_grp {
0053     IPIC_INT_GRP_A = IPIC_SIPRR_A,
0054     IPIC_INT_GRP_D = IPIC_SIPRR_D,
0055     IPIC_MIX_GRP_A = IPIC_SMPRR_A,
0056     IPIC_MIX_GRP_B = IPIC_SMPRR_B,
0057 };
0058
0059 enum ipic_mcp_irq {
0060     IPIC_MCP_IRQ0 = 0,
0061     IPIC_MCP_WDT  = 1,
0062     IPIC_MCP_SBA  = 2,
0063     IPIC_MCP_PCI1 = 5,
0064     IPIC_MCP_PCI2 = 6,
0065     IPIC_MCP_MU   = 7,
0066 };
0067
0068 void __init ipic_set_default_priority(void);
0069 extern u32 ipic_get_mcp_status(void);
0070 extern void ipic_clear_mcp_status(u32 mask);
0071
0072 extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
0073 extern unsigned int ipic_get_irq(void);
0074
0075 #endif /* __ASM_IPIC_H__ */
0076 #endif /* __KERNEL__ */