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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef _ASM_POWERPC_IO_H
0003 #define _ASM_POWERPC_IO_H
0004 #ifdef __KERNEL__
0005 
0006 #define ARCH_HAS_IOREMAP_WC
0007 #ifdef CONFIG_PPC32
0008 #define ARCH_HAS_IOREMAP_WT
0009 #endif
0010 
0011 /*
0012  */
0013 
0014 /* Check of existence of legacy devices */
0015 extern int check_legacy_ioport(unsigned long base_port);
0016 #define I8042_DATA_REG  0x60
0017 #define FDC_BASE    0x3f0
0018 
0019 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
0020 extern struct pci_dev *isa_bridge_pcidev;
0021 /*
0022  * has legacy ISA devices ?
0023  */
0024 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
0025 #endif
0026 
0027 #include <linux/device.h>
0028 #include <linux/compiler.h>
0029 #include <linux/mm.h>
0030 #include <asm/page.h>
0031 #include <asm/byteorder.h>
0032 #include <asm/synch.h>
0033 #include <asm/delay.h>
0034 #include <asm/mmiowb.h>
0035 #include <asm/mmu.h>
0036 
0037 #define SIO_CONFIG_RA   0x398
0038 #define SIO_CONFIG_RD   0x399
0039 
0040 /* 32 bits uses slightly different variables for the various IO
0041  * bases. Most of this file only uses _IO_BASE though which we
0042  * define properly based on the platform
0043  */
0044 #ifndef CONFIG_PCI
0045 #define _IO_BASE    0
0046 #define _ISA_MEM_BASE   0
0047 #define PCI_DRAM_OFFSET 0
0048 #elif defined(CONFIG_PPC32)
0049 #define _IO_BASE    isa_io_base
0050 #define _ISA_MEM_BASE   isa_mem_base
0051 #define PCI_DRAM_OFFSET pci_dram_offset
0052 #else
0053 #define _IO_BASE    pci_io_base
0054 #define _ISA_MEM_BASE   isa_mem_base
0055 #define PCI_DRAM_OFFSET 0
0056 #endif
0057 
0058 extern unsigned long isa_io_base;
0059 extern unsigned long pci_io_base;
0060 extern unsigned long pci_dram_offset;
0061 
0062 extern resource_size_t isa_mem_base;
0063 
0064 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
0065  * is not set or addresses cannot be translated to MMIO. This is typically
0066  * set when the platform supports "special" PIO accesses via a non memory
0067  * mapped mechanism, and allows things like the early udbg UART code to
0068  * function.
0069  */
0070 extern bool isa_io_special;
0071 
0072 #ifdef CONFIG_PPC32
0073 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
0074 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
0075 #endif
0076 #endif
0077 
0078 /*
0079  *
0080  * Low level MMIO accessors
0081  *
0082  * This provides the non-bus specific accessors to MMIO. Those are PowerPC
0083  * specific and thus shouldn't be used in generic code. The accessors
0084  * provided here are:
0085  *
0086  *  in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
0087  *  out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
0088  *  _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
0089  *
0090  * Those operate directly on a kernel virtual address. Note that the prototype
0091  * for the out_* accessors has the arguments in opposite order from the usual
0092  * linux PCI accessors. Unlike those, they take the address first and the value
0093  * next.
0094  *
0095  * Note: I might drop the _ns suffix on the stream operations soon as it is
0096  * simply normal for stream operations to not swap in the first place.
0097  *
0098  */
0099 
0100 #define DEF_MMIO_IN_X(name, size, insn)             \
0101 static inline u##size name(const volatile u##size __iomem *addr)    \
0102 {                                   \
0103     u##size ret;                            \
0104     __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
0105         : "=r" (ret) : "Z" (*addr) : "memory");         \
0106     return ret;                         \
0107 }
0108 
0109 #define DEF_MMIO_OUT_X(name, size, insn)                \
0110 static inline void name(volatile u##size __iomem *addr, u##size val)    \
0111 {                                   \
0112     __asm__ __volatile__("sync;"#insn" %1,%y0"          \
0113         : "=Z" (*addr) : "r" (val) : "memory");         \
0114     mmiowb_set_pending();                       \
0115 }
0116 
0117 #define DEF_MMIO_IN_D(name, size, insn)             \
0118 static inline u##size name(const volatile u##size __iomem *addr)    \
0119 {                                   \
0120     u##size ret;                            \
0121     __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
0122         : "=r" (ret) : "m<>" (*addr) : "memory");   \
0123     return ret;                         \
0124 }
0125 
0126 #define DEF_MMIO_OUT_D(name, size, insn)                \
0127 static inline void name(volatile u##size __iomem *addr, u##size val)    \
0128 {                                   \
0129     __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"         \
0130         : "=m<>" (*addr) : "r" (val) : "memory");   \
0131     mmiowb_set_pending();                       \
0132 }
0133 
0134 DEF_MMIO_IN_D(in_8,     8, lbz);
0135 DEF_MMIO_OUT_D(out_8,   8, stb);
0136 
0137 #ifdef __BIG_ENDIAN__
0138 DEF_MMIO_IN_D(in_be16, 16, lhz);
0139 DEF_MMIO_IN_D(in_be32, 32, lwz);
0140 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
0141 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
0142 
0143 DEF_MMIO_OUT_D(out_be16, 16, sth);
0144 DEF_MMIO_OUT_D(out_be32, 32, stw);
0145 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
0146 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
0147 #else
0148 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
0149 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
0150 DEF_MMIO_IN_D(in_le16, 16, lhz);
0151 DEF_MMIO_IN_D(in_le32, 32, lwz);
0152 
0153 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
0154 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
0155 DEF_MMIO_OUT_D(out_le16, 16, sth);
0156 DEF_MMIO_OUT_D(out_le32, 32, stw);
0157 
0158 #endif /* __BIG_ENDIAN */
0159 
0160 #ifdef __powerpc64__
0161 
0162 #ifdef __BIG_ENDIAN__
0163 DEF_MMIO_OUT_D(out_be64, 64, std);
0164 DEF_MMIO_IN_D(in_be64, 64, ld);
0165 
0166 /* There is no asm instructions for 64 bits reverse loads and stores */
0167 static inline u64 in_le64(const volatile u64 __iomem *addr)
0168 {
0169     return swab64(in_be64(addr));
0170 }
0171 
0172 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
0173 {
0174     out_be64(addr, swab64(val));
0175 }
0176 #else
0177 DEF_MMIO_OUT_D(out_le64, 64, std);
0178 DEF_MMIO_IN_D(in_le64, 64, ld);
0179 
0180 /* There is no asm instructions for 64 bits reverse loads and stores */
0181 static inline u64 in_be64(const volatile u64 __iomem *addr)
0182 {
0183     return swab64(in_le64(addr));
0184 }
0185 
0186 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
0187 {
0188     out_le64(addr, swab64(val));
0189 }
0190 
0191 #endif
0192 #endif /* __powerpc64__ */
0193 
0194 /*
0195  * Low level IO stream instructions are defined out of line for now
0196  */
0197 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
0198 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
0199 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
0200 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
0201 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
0202 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
0203 
0204 /* The _ns naming is historical and will be removed. For now, just #define
0205  * the non _ns equivalent names
0206  */
0207 #define _insw   _insw_ns
0208 #define _insl   _insl_ns
0209 #define _outsw  _outsw_ns
0210 #define _outsl  _outsl_ns
0211 
0212 
0213 /*
0214  * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
0215  */
0216 
0217 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
0218 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
0219                unsigned long n);
0220 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
0221              unsigned long n);
0222 
0223 /*
0224  *
0225  * PCI and standard ISA accessors
0226  *
0227  * Those are globally defined linux accessors for devices on PCI or ISA
0228  * busses. They follow the Linux defined semantics. The current implementation
0229  * for PowerPC is as close as possible to the x86 version of these, and thus
0230  * provides fairly heavy weight barriers for the non-raw versions
0231  *
0232  * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
0233  * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
0234  * own implementation of some or all of the accessors.
0235  */
0236 
0237 /*
0238  * Include the EEH definitions when EEH is enabled only so they don't get
0239  * in the way when building for 32 bits
0240  */
0241 #ifdef CONFIG_EEH
0242 #include <asm/eeh.h>
0243 #endif
0244 
0245 /* Shortcut to the MMIO argument pointer */
0246 #define PCI_IO_ADDR volatile void __iomem *
0247 
0248 /* Indirect IO address tokens:
0249  *
0250  * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
0251  * on all MMIOs. (Note that this is all 64 bits only for now)
0252  *
0253  * To help platforms who may need to differentiate MMIO addresses in
0254  * their hooks, a bitfield is reserved for use by the platform near the
0255  * top of MMIO addresses (not PIO, those have to cope the hard way).
0256  *
0257  * The highest address in the kernel virtual space are:
0258  *
0259  *  d0003fffffffffff    # with Hash MMU
0260  *  c00fffffffffffff    # with Radix MMU
0261  *
0262  * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
0263  * that can be used for the field.
0264  *
0265  * The direct IO mapping operations will then mask off those bits
0266  * before doing the actual access, though that only happen when
0267  * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
0268  * mechanism
0269  *
0270  * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
0271  * all PIO functions call through a hook.
0272  */
0273 
0274 #ifdef CONFIG_PPC_INDIRECT_MMIO
0275 #define PCI_IO_IND_TOKEN_SHIFT  52
0276 #define PCI_IO_IND_TOKEN_MASK   (0xfful << PCI_IO_IND_TOKEN_SHIFT)
0277 #define PCI_FIX_ADDR(addr)                      \
0278     ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
0279 #define PCI_GET_ADDR_TOKEN(addr)                    \
0280     (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>         \
0281         PCI_IO_IND_TOKEN_SHIFT)
0282 #define PCI_SET_ADDR_TOKEN(addr, token)                 \
0283 do {                                    \
0284     unsigned long __a = (unsigned long)(addr);          \
0285     __a &= ~PCI_IO_IND_TOKEN_MASK;                  \
0286     __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;  \
0287     (addr) = (void __iomem *)__a;                   \
0288 } while(0)
0289 #else
0290 #define PCI_FIX_ADDR(addr) (addr)
0291 #endif
0292 
0293 
0294 /*
0295  * Non ordered and non-swapping "raw" accessors
0296  */
0297 
0298 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
0299 {
0300     return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
0301 }
0302 #define __raw_readb __raw_readb
0303 
0304 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
0305 {
0306     return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
0307 }
0308 #define __raw_readw __raw_readw
0309 
0310 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
0311 {
0312     return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
0313 }
0314 #define __raw_readl __raw_readl
0315 
0316 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
0317 {
0318     *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
0319 }
0320 #define __raw_writeb __raw_writeb
0321 
0322 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
0323 {
0324     *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
0325 }
0326 #define __raw_writew __raw_writew
0327 
0328 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
0329 {
0330     *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
0331 }
0332 #define __raw_writel __raw_writel
0333 
0334 #ifdef __powerpc64__
0335 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
0336 {
0337     return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
0338 }
0339 #define __raw_readq __raw_readq
0340 
0341 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
0342 {
0343     *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
0344 }
0345 #define __raw_writeq __raw_writeq
0346 
0347 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
0348 {
0349     __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
0350 }
0351 #define __raw_writeq_be __raw_writeq_be
0352 
0353 /*
0354  * Real mode versions of the above. Those instructions are only supposed
0355  * to be used in hypervisor real mode as per the architecture spec.
0356  */
0357 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
0358 {
0359     __asm__ __volatile__(".machine push;   \
0360                   .machine power6; \
0361                   stbcix %0,0,%1;  \
0362                   .machine pop;"
0363         : : "r" (val), "r" (paddr) : "memory");
0364 }
0365 
0366 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
0367 {
0368     __asm__ __volatile__(".machine push;   \
0369                   .machine power6; \
0370                   sthcix %0,0,%1;  \
0371                   .machine pop;"
0372         : : "r" (val), "r" (paddr) : "memory");
0373 }
0374 
0375 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
0376 {
0377     __asm__ __volatile__(".machine push;   \
0378                   .machine power6; \
0379                   stwcix %0,0,%1;  \
0380                   .machine pop;"
0381         : : "r" (val), "r" (paddr) : "memory");
0382 }
0383 
0384 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
0385 {
0386     __asm__ __volatile__(".machine push;   \
0387                   .machine power6; \
0388                   stdcix %0,0,%1;  \
0389                   .machine pop;"
0390         : : "r" (val), "r" (paddr) : "memory");
0391 }
0392 
0393 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
0394 {
0395     __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
0396 }
0397 
0398 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
0399 {
0400     u8 ret;
0401     __asm__ __volatile__(".machine push;   \
0402                   .machine power6; \
0403                   lbzcix %0,0, %1; \
0404                   .machine pop;"
0405                  : "=r" (ret) : "r" (paddr) : "memory");
0406     return ret;
0407 }
0408 
0409 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
0410 {
0411     u16 ret;
0412     __asm__ __volatile__(".machine push;   \
0413                   .machine power6; \
0414                   lhzcix %0,0, %1; \
0415                   .machine pop;"
0416                  : "=r" (ret) : "r" (paddr) : "memory");
0417     return ret;
0418 }
0419 
0420 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
0421 {
0422     u32 ret;
0423     __asm__ __volatile__(".machine push;   \
0424                   .machine power6; \
0425                   lwzcix %0,0, %1; \
0426                   .machine pop;"
0427                  : "=r" (ret) : "r" (paddr) : "memory");
0428     return ret;
0429 }
0430 
0431 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
0432 {
0433     u64 ret;
0434     __asm__ __volatile__(".machine push;   \
0435                   .machine power6; \
0436                   ldcix %0,0, %1;  \
0437                   .machine pop;"
0438                  : "=r" (ret) : "r" (paddr) : "memory");
0439     return ret;
0440 }
0441 #endif /* __powerpc64__ */
0442 
0443 /*
0444  *
0445  * PCI PIO and MMIO accessors.
0446  *
0447  *
0448  * On 32 bits, PIO operations have a recovery mechanism in case they trigger
0449  * machine checks (which they occasionally do when probing non existing
0450  * IO ports on some platforms, like PowerMac and 8xx).
0451  * I always found it to be of dubious reliability and I am tempted to get
0452  * rid of it one of these days. So if you think it's important to keep it,
0453  * please voice up asap. We never had it for 64 bits and I do not intend
0454  * to port it over
0455  */
0456 
0457 #ifdef CONFIG_PPC32
0458 
0459 #define __do_in_asm(name, op)               \
0460 static inline unsigned int name(unsigned int port)  \
0461 {                           \
0462     unsigned int x;                 \
0463     __asm__ __volatile__(               \
0464         "sync\n"                \
0465         "0:"    op "    %0,0,%1\n"      \
0466         "1: twi 0,%0,0\n"       \
0467         "2: isync\n"            \
0468         "3: nop\n"              \
0469         "4:\n"                  \
0470         ".section .fixup,\"ax\"\n"      \
0471         "5: li  %0,-1\n"        \
0472         "   b   4b\n"           \
0473         ".previous\n"               \
0474         EX_TABLE(0b, 5b)            \
0475         EX_TABLE(1b, 5b)            \
0476         EX_TABLE(2b, 5b)            \
0477         EX_TABLE(3b, 5b)            \
0478         : "=&r" (x)             \
0479         : "r" (port + _IO_BASE)         \
0480         : "memory");                \
0481     return x;                   \
0482 }
0483 
0484 #define __do_out_asm(name, op)              \
0485 static inline void name(unsigned int val, unsigned int port) \
0486 {                           \
0487     __asm__ __volatile__(               \
0488         "sync\n"                \
0489         "0:" op " %0,0,%1\n"            \
0490         "1: sync\n"             \
0491         "2:\n"                  \
0492         EX_TABLE(0b, 2b)            \
0493         EX_TABLE(1b, 2b)            \
0494         : : "r" (val), "r" (port + _IO_BASE)    \
0495         : "memory");                \
0496 }
0497 
0498 __do_in_asm(_rec_inb, "lbzx")
0499 __do_in_asm(_rec_inw, "lhbrx")
0500 __do_in_asm(_rec_inl, "lwbrx")
0501 __do_out_asm(_rec_outb, "stbx")
0502 __do_out_asm(_rec_outw, "sthbrx")
0503 __do_out_asm(_rec_outl, "stwbrx")
0504 
0505 #endif /* CONFIG_PPC32 */
0506 
0507 /* The "__do_*" operations below provide the actual "base" implementation
0508  * for each of the defined accessors. Some of them use the out_* functions
0509  * directly, some of them still use EEH, though we might change that in the
0510  * future. Those macros below provide the necessary argument swapping and
0511  * handling of the IO base for PIO.
0512  *
0513  * They are themselves used by the macros that define the actual accessors
0514  * and can be used by the hooks if any.
0515  *
0516  * Note that PIO operations are always defined in terms of their corresonding
0517  * MMIO operations. That allows platforms like iSeries who want to modify the
0518  * behaviour of both to only hook on the MMIO version and get both. It's also
0519  * possible to hook directly at the toplevel PIO operation if they have to
0520  * be handled differently
0521  */
0522 #define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
0523 #define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
0524 #define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
0525 #define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
0526 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
0527 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
0528 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
0529 
0530 #ifdef CONFIG_EEH
0531 #define __do_readb(addr)    eeh_readb(PCI_FIX_ADDR(addr))
0532 #define __do_readw(addr)    eeh_readw(PCI_FIX_ADDR(addr))
0533 #define __do_readl(addr)    eeh_readl(PCI_FIX_ADDR(addr))
0534 #define __do_readq(addr)    eeh_readq(PCI_FIX_ADDR(addr))
0535 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
0536 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
0537 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
0538 #else /* CONFIG_EEH */
0539 #define __do_readb(addr)    in_8(PCI_FIX_ADDR(addr))
0540 #define __do_readw(addr)    in_le16(PCI_FIX_ADDR(addr))
0541 #define __do_readl(addr)    in_le32(PCI_FIX_ADDR(addr))
0542 #define __do_readq(addr)    in_le64(PCI_FIX_ADDR(addr))
0543 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
0544 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
0545 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
0546 #endif /* !defined(CONFIG_EEH) */
0547 
0548 #ifdef CONFIG_PPC32
0549 #define __do_outb(val, port)    _rec_outb(val, port)
0550 #define __do_outw(val, port)    _rec_outw(val, port)
0551 #define __do_outl(val, port)    _rec_outl(val, port)
0552 #define __do_inb(port)      _rec_inb(port)
0553 #define __do_inw(port)      _rec_inw(port)
0554 #define __do_inl(port)      _rec_inl(port)
0555 #else /* CONFIG_PPC32 */
0556 #define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
0557 #define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
0558 #define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
0559 #define __do_inb(port)      readb((PCI_IO_ADDR)_IO_BASE + port);
0560 #define __do_inw(port)      readw((PCI_IO_ADDR)_IO_BASE + port);
0561 #define __do_inl(port)      readl((PCI_IO_ADDR)_IO_BASE + port);
0562 #endif /* !CONFIG_PPC32 */
0563 
0564 #ifdef CONFIG_EEH
0565 #define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
0566 #define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
0567 #define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
0568 #else /* CONFIG_EEH */
0569 #define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
0570 #define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
0571 #define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
0572 #endif /* !CONFIG_EEH */
0573 #define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
0574 #define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
0575 #define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
0576 
0577 #define __do_insb(p, b, n)  readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
0578 #define __do_insw(p, b, n)  readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
0579 #define __do_insl(p, b, n)  readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
0580 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
0581 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
0582 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
0583 
0584 #define __do_memset_io(addr, c, n)  \
0585                 _memset_io(PCI_FIX_ADDR(addr), c, n)
0586 #define __do_memcpy_toio(dst, src, n)   \
0587                 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
0588 
0589 #ifdef CONFIG_EEH
0590 #define __do_memcpy_fromio(dst, src, n) \
0591                 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
0592 #else /* CONFIG_EEH */
0593 #define __do_memcpy_fromio(dst, src, n) \
0594                 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
0595 #endif /* !CONFIG_EEH */
0596 
0597 #ifdef CONFIG_PPC_INDIRECT_PIO
0598 #define DEF_PCI_HOOK_pio(x) x
0599 #else
0600 #define DEF_PCI_HOOK_pio(x) NULL
0601 #endif
0602 
0603 #ifdef CONFIG_PPC_INDIRECT_MMIO
0604 #define DEF_PCI_HOOK_mem(x) x
0605 #else
0606 #define DEF_PCI_HOOK_mem(x) NULL
0607 #endif
0608 
0609 /* Structure containing all the hooks */
0610 extern struct ppc_pci_io {
0611 
0612 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
0613 #define DEF_PCI_AC_NORET(name, at, al, space, aa)   void (*name) at;
0614 
0615 #include <asm/io-defs.h>
0616 
0617 #undef DEF_PCI_AC_RET
0618 #undef DEF_PCI_AC_NORET
0619 
0620 } ppc_pci_io;
0621 
0622 /* The inline wrappers */
0623 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa)        \
0624 static inline ret name at                   \
0625 {                               \
0626     if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)  \
0627         return ppc_pci_io.name al;          \
0628     return __do_##name al;                  \
0629 }
0630 
0631 #define DEF_PCI_AC_NORET(name, at, al, space, aa)       \
0632 static inline void name at                  \
0633 {                               \
0634     if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL)      \
0635         ppc_pci_io.name al;             \
0636     else                            \
0637         __do_##name al;                 \
0638 }
0639 
0640 #include <asm/io-defs.h>
0641 
0642 #undef DEF_PCI_AC_RET
0643 #undef DEF_PCI_AC_NORET
0644 
0645 /* Some drivers check for the presence of readq & writeq with
0646  * a #ifdef, so we make them happy here.
0647  */
0648 #define readb readb
0649 #define readw readw
0650 #define readl readl
0651 #define writeb writeb
0652 #define writew writew
0653 #define writel writel
0654 #define readsb readsb
0655 #define readsw readsw
0656 #define readsl readsl
0657 #define writesb writesb
0658 #define writesw writesw
0659 #define writesl writesl
0660 #define inb inb
0661 #define inw inw
0662 #define inl inl
0663 #define outb outb
0664 #define outw outw
0665 #define outl outl
0666 #define insb insb
0667 #define insw insw
0668 #define insl insl
0669 #define outsb outsb
0670 #define outsw outsw
0671 #define outsl outsl
0672 #ifdef __powerpc64__
0673 #define readq   readq
0674 #define writeq  writeq
0675 #endif
0676 #define memset_io memset_io
0677 #define memcpy_fromio memcpy_fromio
0678 #define memcpy_toio memcpy_toio
0679 
0680 /*
0681  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
0682  * access
0683  */
0684 #define xlate_dev_mem_ptr(p)    __va(p)
0685 
0686 /*
0687  * We don't do relaxed operations yet, at least not with this semantic
0688  */
0689 #define readb_relaxed(addr) readb(addr)
0690 #define readw_relaxed(addr) readw(addr)
0691 #define readl_relaxed(addr) readl(addr)
0692 #define readq_relaxed(addr) readq(addr)
0693 #define writeb_relaxed(v, addr) writeb(v, addr)
0694 #define writew_relaxed(v, addr) writew(v, addr)
0695 #define writel_relaxed(v, addr) writel(v, addr)
0696 #define writeq_relaxed(v, addr) writeq(v, addr)
0697 
0698 #ifdef CONFIG_GENERIC_IOMAP
0699 #include <asm-generic/iomap.h>
0700 #else
0701 /*
0702  * Here comes the implementation of the IOMAP interfaces.
0703  */
0704 static inline unsigned int ioread16be(const void __iomem *addr)
0705 {
0706     return readw_be(addr);
0707 }
0708 #define ioread16be ioread16be
0709 
0710 static inline unsigned int ioread32be(const void __iomem *addr)
0711 {
0712     return readl_be(addr);
0713 }
0714 #define ioread32be ioread32be
0715 
0716 #ifdef __powerpc64__
0717 static inline u64 ioread64_lo_hi(const void __iomem *addr)
0718 {
0719     return readq(addr);
0720 }
0721 #define ioread64_lo_hi ioread64_lo_hi
0722 
0723 static inline u64 ioread64_hi_lo(const void __iomem *addr)
0724 {
0725     return readq(addr);
0726 }
0727 #define ioread64_hi_lo ioread64_hi_lo
0728 
0729 static inline u64 ioread64be(const void __iomem *addr)
0730 {
0731     return readq_be(addr);
0732 }
0733 #define ioread64be ioread64be
0734 
0735 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
0736 {
0737     return readq_be(addr);
0738 }
0739 #define ioread64be_lo_hi ioread64be_lo_hi
0740 
0741 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
0742 {
0743     return readq_be(addr);
0744 }
0745 #define ioread64be_hi_lo ioread64be_hi_lo
0746 #endif /* __powerpc64__ */
0747 
0748 static inline void iowrite16be(u16 val, void __iomem *addr)
0749 {
0750     writew_be(val, addr);
0751 }
0752 #define iowrite16be iowrite16be
0753 
0754 static inline void iowrite32be(u32 val, void __iomem *addr)
0755 {
0756     writel_be(val, addr);
0757 }
0758 #define iowrite32be iowrite32be
0759 
0760 #ifdef __powerpc64__
0761 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
0762 {
0763     writeq(val, addr);
0764 }
0765 #define iowrite64_lo_hi iowrite64_lo_hi
0766 
0767 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
0768 {
0769     writeq(val, addr);
0770 }
0771 #define iowrite64_hi_lo iowrite64_hi_lo
0772 
0773 static inline void iowrite64be(u64 val, void __iomem *addr)
0774 {
0775     writeq_be(val, addr);
0776 }
0777 #define iowrite64be iowrite64be
0778 
0779 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
0780 {
0781     writeq_be(val, addr);
0782 }
0783 #define iowrite64be_lo_hi iowrite64be_lo_hi
0784 
0785 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
0786 {
0787     writeq_be(val, addr);
0788 }
0789 #define iowrite64be_hi_lo iowrite64be_hi_lo
0790 #endif /* __powerpc64__ */
0791 
0792 struct pci_dev;
0793 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
0794 #define pci_iounmap pci_iounmap
0795 void __iomem *ioport_map(unsigned long port, unsigned int len);
0796 #define ioport_map ioport_map
0797 #endif
0798 
0799 static inline void iosync(void)
0800 {
0801         __asm__ __volatile__ ("sync" : : : "memory");
0802 }
0803 
0804 /* Enforce in-order execution of data I/O.
0805  * No distinction between read/write on PPC; use eieio for all three.
0806  * Those are fairly week though. They don't provide a barrier between
0807  * MMIO and cacheable storage nor do they provide a barrier vs. locks,
0808  * they only provide barriers between 2 __raw MMIO operations and
0809  * possibly break write combining.
0810  */
0811 #define iobarrier_rw() eieio()
0812 #define iobarrier_r()  eieio()
0813 #define iobarrier_w()  eieio()
0814 
0815 
0816 /*
0817  * output pause versions need a delay at least for the
0818  * w83c105 ide controller in a p610.
0819  */
0820 #define inb_p(port)             inb(port)
0821 #define outb_p(val, port)       (udelay(1), outb((val), (port)))
0822 #define inw_p(port)             inw(port)
0823 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
0824 #define inl_p(port)             inl(port)
0825 #define outl_p(val, port)       (udelay(1), outl((val), (port)))
0826 
0827 
0828 #define IO_SPACE_LIMIT ~(0UL)
0829 
0830 /**
0831  * ioremap     -   map bus memory into CPU space
0832  * @address:   bus address of the memory
0833  * @size:      size of the resource to map
0834  *
0835  * ioremap performs a platform specific sequence of operations to
0836  * make bus memory CPU accessible via the readb/readw/readl/writeb/
0837  * writew/writel functions and the other mmio helpers. The returned
0838  * address is not guaranteed to be usable directly as a virtual
0839  * address.
0840  *
0841  * We provide a few variations of it:
0842  *
0843  * * ioremap is the standard one and provides non-cacheable guarded mappings
0844  *   and can be hooked by the platform via ppc_md
0845  *
0846  * * ioremap_prot allows to specify the page flags as an argument and can
0847  *   also be hooked by the platform via ppc_md.
0848  *
0849  * * ioremap_wc enables write combining
0850  *
0851  * * ioremap_wt enables write through
0852  *
0853  * * ioremap_coherent maps coherent cached memory
0854  *
0855  * * iounmap undoes such a mapping and can be hooked
0856  *
0857  * * __ioremap_caller is the same as above but takes an explicit caller
0858  *   reference rather than using __builtin_return_address(0)
0859  *
0860  */
0861 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
0862 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
0863                   unsigned long flags);
0864 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
0865 #define ioremap_wc ioremap_wc
0866 
0867 #ifdef CONFIG_PPC32
0868 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
0869 #define ioremap_wt ioremap_wt
0870 #endif
0871 
0872 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
0873 #define ioremap_uc(addr, size)      ioremap((addr), (size))
0874 #define ioremap_cache(addr, size) \
0875     ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
0876 
0877 extern void iounmap(volatile void __iomem *addr);
0878 
0879 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
0880 
0881 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
0882             unsigned long size, pgprot_t prot);
0883 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
0884              pgprot_t prot, void *caller);
0885 
0886 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
0887                       pgprot_t prot, void *caller);
0888 
0889 /*
0890  * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
0891  * which needs some additional definitions here. They basically allow PIO
0892  * space overall to be 1GB. This will work as long as we never try to use
0893  * iomap to map MMIO below 1GB which should be fine on ppc64
0894  */
0895 #define HAVE_ARCH_PIO_SIZE      1
0896 #define PIO_OFFSET          0x00000000UL
0897 #define PIO_MASK            (FULL_IO_SIZE - 1)
0898 #define PIO_RESERVED            (FULL_IO_SIZE)
0899 
0900 #define mmio_read16be(addr)     readw_be(addr)
0901 #define mmio_read32be(addr)     readl_be(addr)
0902 #define mmio_read64be(addr)     readq_be(addr)
0903 #define mmio_write16be(val, addr)   writew_be(val, addr)
0904 #define mmio_write32be(val, addr)   writel_be(val, addr)
0905 #define mmio_write64be(val, addr)   writeq_be(val, addr)
0906 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
0907 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
0908 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
0909 #define mmio_outsb(addr, src, count)    writesb(addr, src, count)
0910 #define mmio_outsw(addr, src, count)    writesw(addr, src, count)
0911 #define mmio_outsl(addr, src, count)    writesl(addr, src, count)
0912 
0913 /**
0914  *  virt_to_phys    -   map virtual addresses to physical
0915  *  @address: address to remap
0916  *
0917  *  The returned physical address is the physical (CPU) mapping for
0918  *  the memory address given. It is only valid to use this function on
0919  *  addresses directly mapped or allocated via kmalloc.
0920  *
0921  *  This function does not give bus mappings for DMA transfers. In
0922  *  almost all conceivable cases a device driver should not be using
0923  *  this function
0924  */
0925 static inline unsigned long virt_to_phys(volatile void * address)
0926 {
0927     WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
0928 
0929     return __pa((unsigned long)address);
0930 }
0931 #define virt_to_phys virt_to_phys
0932 
0933 /**
0934  *  phys_to_virt    -   map physical address to virtual
0935  *  @address: address to remap
0936  *
0937  *  The returned virtual address is a current CPU mapping for
0938  *  the memory address given. It is only valid to use this function on
0939  *  addresses that have a kernel mapping
0940  *
0941  *  This function does not handle bus mappings for DMA transfers. In
0942  *  almost all conceivable cases a device driver should not be using
0943  *  this function
0944  */
0945 static inline void * phys_to_virt(unsigned long address)
0946 {
0947     return (void *)__va(address);
0948 }
0949 #define phys_to_virt phys_to_virt
0950 
0951 /*
0952  * Change "struct page" to physical address.
0953  */
0954 static inline phys_addr_t page_to_phys(struct page *page)
0955 {
0956     unsigned long pfn = page_to_pfn(page);
0957 
0958     WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
0959 
0960     return PFN_PHYS(pfn);
0961 }
0962 
0963 /*
0964  * 32 bits still uses virt_to_bus() for it's implementation of DMA
0965  * mappings se we have to keep it defined here. We also have some old
0966  * drivers (shame shame shame) that use bus_to_virt() and haven't been
0967  * fixed yet so I need to define it here.
0968  */
0969 #ifdef CONFIG_PPC32
0970 
0971 static inline unsigned long virt_to_bus(volatile void * address)
0972 {
0973         if (address == NULL)
0974         return 0;
0975         return __pa(address) + PCI_DRAM_OFFSET;
0976 }
0977 #define virt_to_bus virt_to_bus
0978 
0979 static inline void * bus_to_virt(unsigned long address)
0980 {
0981         if (address == 0)
0982         return NULL;
0983         return __va(address - PCI_DRAM_OFFSET);
0984 }
0985 #define bus_to_virt bus_to_virt
0986 
0987 #endif /* CONFIG_PPC32 */
0988 
0989 /* access ports */
0990 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
0991 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
0992 
0993 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
0994 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
0995 
0996 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
0997 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
0998 
0999 /* Clear and set bits in one shot.  These macros can be used to clear and
1000  * set multiple bits in a register using a single read-modify-write.  These
1001  * macros can also be used to set a multiple-bit bit pattern using a mask,
1002  * by specifying the mask in the 'clear' parameter and the new bit pattern
1003  * in the 'set' parameter.
1004  */
1005 
1006 #define clrsetbits(type, addr, clear, set) \
1007     out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1008 
1009 #ifdef __powerpc64__
1010 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1011 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1012 #endif
1013 
1014 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1015 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1016 
1017 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1018 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1019 
1020 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1021 
1022 #include <asm-generic/io.h>
1023 
1024 #endif /* __KERNEL__ */
1025 
1026 #endif /* _ASM_POWERPC_IO_H */
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