include/asm/immap_cpm2.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * CPM2 Internal Memory Map
0004  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
0005  *
0006  * The Internal Memory Map for devices with CPM2 on them.  This
0007  * is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
0008  * 8560).
0009  */
0010 #ifdef __KERNEL__
0011 #ifndef __IMMAP_CPM2__
0012 #define __IMMAP_CPM2__
0013
0014 #include <linux/types.h>
0015
0016 /* System configuration registers.
0017 */
0018 typedef struct sys_82xx_conf {
0019     u32 sc_siumcr;
0020     u32 sc_sypcr;
0021     u8  res1[6];
0022     u16 sc_swsr;
0023     u8  res2[20];
0024     u32 sc_bcr;
0025     u8  sc_ppc_acr;
0026     u8  res3[3];
0027     u32 sc_ppc_alrh;
0028     u32 sc_ppc_alrl;
0029     u8  sc_lcl_acr;
0030     u8  res4[3];
0031     u32 sc_lcl_alrh;
0032     u32 sc_lcl_alrl;
0033     u32 sc_tescr1;
0034     u32 sc_tescr2;
0035     u32 sc_ltescr1;
0036     u32 sc_ltescr2;
0037     u32 sc_pdtea;
0038     u8  sc_pdtem;
0039     u8  res5[3];
0040     u32 sc_ldtea;
0041     u8  sc_ldtem;
0042     u8  res6[163];
0043 } sysconf_82xx_cpm2_t;
0044
0045 typedef struct sys_85xx_conf {
0046     u32 sc_cear;
0047     u16 sc_ceer;
0048     u16 sc_cemr;
0049     u8  res1[70];
0050     u32 sc_smaer;
0051     u8  res2[4];
0052     u32 sc_smevr;
0053     u32 sc_smctr;
0054     u32 sc_lmaer;
0055     u8  res3[4];
0056     u32 sc_lmevr;
0057     u32 sc_lmctr;
0058     u8  res4[144];
0059 } sysconf_85xx_cpm2_t;
0060
0061 typedef union sys_conf {
0062     sysconf_82xx_cpm2_t siu_82xx;
0063     sysconf_85xx_cpm2_t siu_85xx;
0064 } sysconf_cpm2_t;
0065
0066
0067
0068 /* Memory controller registers.
0069 */
0070 typedef struct  mem_ctlr {
0071     u32 memc_br0;
0072     u32 memc_or0;
0073     u32 memc_br1;
0074     u32 memc_or1;
0075     u32 memc_br2;
0076     u32 memc_or2;
0077     u32 memc_br3;
0078     u32 memc_or3;
0079     u32 memc_br4;
0080     u32 memc_or4;
0081     u32 memc_br5;
0082     u32 memc_or5;
0083     u32 memc_br6;
0084     u32 memc_or6;
0085     u32 memc_br7;
0086     u32 memc_or7;
0087     u32 memc_br8;
0088     u32 memc_or8;
0089     u32 memc_br9;
0090     u32 memc_or9;
0091     u32 memc_br10;
0092     u32 memc_or10;
0093     u32 memc_br11;
0094     u32 memc_or11;
0095     u8  res1[8];
0096     u32 memc_mar;
0097     u8  res2[4];
0098     u32 memc_mamr;
0099     u32 memc_mbmr;
0100     u32 memc_mcmr;
0101     u8  res3[8];
0102     u16 memc_mptpr;
0103     u8  res4[2];
0104     u32 memc_mdr;
0105     u8  res5[4];
0106     u32 memc_psdmr;
0107     u32 memc_lsdmr;
0108     u8  memc_purt;
0109     u8  res6[3];
0110     u8  memc_psrt;
0111     u8  res7[3];
0112     u8  memc_lurt;
0113     u8  res8[3];
0114     u8  memc_lsrt;
0115     u8  res9[3];
0116     u32 memc_immr;
0117     u32 memc_pcibr0;
0118     u32 memc_pcibr1;
0119     u8  res10[16];
0120     u32 memc_pcimsk0;
0121     u32 memc_pcimsk1;
0122     u8  res11[52];
0123 } memctl_cpm2_t;
0124
0125 /* System Integration Timers.
0126 */
0127 typedef struct  sys_int_timers {
0128     u8  res1[32];
0129     u16 sit_tmcntsc;
0130     u8  res2[2];
0131     u32 sit_tmcnt;
0132     u8  res3[4];
0133     u32 sit_tmcntal;
0134     u8  res4[16];
0135     u16 sit_piscr;
0136     u8  res5[2];
0137     u32 sit_pitc;
0138     u32 sit_pitr;
0139     u8      res6[94];
0140     u8  res7[390];
0141 } sit_cpm2_t;
0142
0143 #define PISCR_PIRQ_MASK     ((u16)0xff00)
0144 #define PISCR_PS        ((u16)0x0080)
0145 #define PISCR_PIE       ((u16)0x0004)
0146 #define PISCR_PTF       ((u16)0x0002)
0147 #define PISCR_PTE       ((u16)0x0001)
0148
0149 /* PCI Controller.
0150 */
0151 typedef struct pci_ctlr {
0152     u32 pci_omisr;
0153     u32 pci_omimr;
0154     u8  res1[8];
0155     u32 pci_ifqpr;
0156     u32 pci_ofqpr;
0157     u8  res2[8];
0158     u32 pci_imr0;
0159     u32 pci_imr1;
0160     u32 pci_omr0;
0161     u32 pci_omr1;
0162     u32 pci_odr;
0163     u8  res3[4];
0164     u32 pci_idr;
0165     u8  res4[20];
0166     u32 pci_imisr;
0167     u32 pci_imimr;
0168     u8  res5[24];
0169     u32 pci_ifhpr;
0170     u8  res6[4];
0171     u32 pci_iftpr;
0172     u8  res7[4];
0173     u32 pci_iphpr;
0174     u8  res8[4];
0175     u32 pci_iptpr;
0176     u8  res9[4];
0177     u32 pci_ofhpr;
0178     u8  res10[4];
0179     u32 pci_oftpr;
0180     u8  res11[4];
0181     u32 pci_ophpr;
0182     u8  res12[4];
0183     u32 pci_optpr;
0184     u8  res13[8];
0185     u32 pci_mucr;
0186     u8  res14[8];
0187     u32 pci_qbar;
0188     u8  res15[12];
0189     u32 pci_dmamr0;
0190     u32 pci_dmasr0;
0191     u32 pci_dmacdar0;
0192     u8  res16[4];
0193     u32 pci_dmasar0;
0194     u8  res17[4];
0195     u32 pci_dmadar0;
0196     u8  res18[4];
0197     u32 pci_dmabcr0;
0198     u32 pci_dmandar0;
0199     u8  res19[86];
0200     u32 pci_dmamr1;
0201     u32 pci_dmasr1;
0202     u32 pci_dmacdar1;
0203     u8  res20[4];
0204     u32 pci_dmasar1;
0205     u8  res21[4];
0206     u32 pci_dmadar1;
0207     u8  res22[4];
0208     u32 pci_dmabcr1;
0209     u32 pci_dmandar1;
0210     u8  res23[88];
0211     u32 pci_dmamr2;
0212     u32 pci_dmasr2;
0213     u32 pci_dmacdar2;
0214     u8  res24[4];
0215     u32 pci_dmasar2;
0216     u8  res25[4];
0217     u32 pci_dmadar2;
0218     u8  res26[4];
0219     u32 pci_dmabcr2;
0220     u32 pci_dmandar2;
0221     u8  res27[88];
0222     u32 pci_dmamr3;
0223     u32 pci_dmasr3;
0224     u32 pci_dmacdar3;
0225     u8  res28[4];
0226     u32 pci_dmasar3;
0227     u8  res29[4];
0228     u32 pci_dmadar3;
0229     u8  res30[4];
0230     u32 pci_dmabcr3;
0231     u32 pci_dmandar3;
0232     u8  res31[344];
0233     u32 pci_potar0;
0234     u8  res32[4];
0235     u32 pci_pobar0;
0236     u8  res33[4];
0237     u32 pci_pocmr0;
0238     u8  res34[4];
0239     u32 pci_potar1;
0240     u8  res35[4];
0241     u32 pci_pobar1;
0242     u8  res36[4];
0243     u32 pci_pocmr1;
0244     u8  res37[4];
0245     u32 pci_potar2;
0246     u8  res38[4];
0247     u32 pci_pobar2;
0248     u8  res39[4];
0249     u32 pci_pocmr2;
0250     u8  res40[50];
0251     u32 pci_ptcr;
0252     u32 pci_gpcr;
0253     u32 pci_gcr;
0254     u32 pci_esr;
0255     u32 pci_emr;
0256     u32 pci_ecr;
0257     u32 pci_eacr;
0258     u8  res41[4];
0259     u32 pci_edcr;
0260     u8  res42[4];
0261     u32 pci_eccr;
0262     u8  res43[44];
0263     u32 pci_pitar1;
0264     u8  res44[4];
0265     u32 pci_pibar1;
0266     u8  res45[4];
0267     u32 pci_picmr1;
0268     u8  res46[4];
0269     u32 pci_pitar0;
0270     u8  res47[4];
0271     u32 pci_pibar0;
0272     u8  res48[4];
0273     u32 pci_picmr0;
0274     u8  res49[4];
0275     u32 pci_cfg_addr;
0276     u32 pci_cfg_data;
0277     u32 pci_int_ack;
0278     u8  res50[756];
0279 } pci_cpm2_t;
0280
0281 /* Interrupt Controller.
0282 */
0283 typedef struct interrupt_controller {
0284     u16 ic_sicr;
0285     u8  res1[2];
0286     u32 ic_sivec;
0287     u32 ic_sipnrh;
0288     u32 ic_sipnrl;
0289     u32 ic_siprr;
0290     u32 ic_scprrh;
0291     u32 ic_scprrl;
0292     u32 ic_simrh;
0293     u32 ic_simrl;
0294     u32 ic_siexr;
0295     u8  res2[88];
0296 } intctl_cpm2_t;
0297
0298 /* Clocks and Reset.
0299 */
0300 typedef struct clk_and_reset {
0301     u32 car_sccr;
0302     u8  res1[4];
0303     u32 car_scmr;
0304     u8  res2[4];
0305     u32 car_rsr;
0306     u32 car_rmr;
0307     u8  res[104];
0308 } car_cpm2_t;
0309
0310 /* Input/Output Port control/status registers.
0311  * Names consistent with processor manual, although they are different
0312  * from the original 8xx names.......
0313  */
0314 typedef struct io_port {
0315     u32 iop_pdira;
0316     u32 iop_ppara;
0317     u32 iop_psora;
0318     u32 iop_podra;
0319     u32 iop_pdata;
0320     u8  res1[12];
0321     u32 iop_pdirb;
0322     u32 iop_pparb;
0323     u32 iop_psorb;
0324     u32 iop_podrb;
0325     u32 iop_pdatb;
0326     u8  res2[12];
0327     u32 iop_pdirc;
0328     u32 iop_pparc;
0329     u32 iop_psorc;
0330     u32 iop_podrc;
0331     u32 iop_pdatc;
0332     u8  res3[12];
0333     u32 iop_pdird;
0334     u32 iop_ppard;
0335     u32 iop_psord;
0336     u32 iop_podrd;
0337     u32 iop_pdatd;
0338     u8  res4[12];
0339 } iop_cpm2_t;
0340
0341 /* Communication Processor Module Timers
0342 */
0343 typedef struct cpm_timers {
0344     u8  cpmt_tgcr1;
0345     u8  res1[3];
0346     u8  cpmt_tgcr2;
0347     u8  res2[11];
0348     u16 cpmt_tmr1;
0349     u16 cpmt_tmr2;
0350     u16 cpmt_trr1;
0351     u16 cpmt_trr2;
0352     u16 cpmt_tcr1;
0353     u16 cpmt_tcr2;
0354     u16 cpmt_tcn1;
0355     u16 cpmt_tcn2;
0356     u16 cpmt_tmr3;
0357     u16 cpmt_tmr4;
0358     u16 cpmt_trr3;
0359     u16 cpmt_trr4;
0360     u16 cpmt_tcr3;
0361     u16 cpmt_tcr4;
0362     u16 cpmt_tcn3;
0363     u16 cpmt_tcn4;
0364     u16 cpmt_ter1;
0365     u16 cpmt_ter2;
0366     u16 cpmt_ter3;
0367     u16 cpmt_ter4;
0368     u8  res3[584];
0369 } cpmtimer_cpm2_t;
0370
0371 /* DMA control/status registers.
0372 */
0373 typedef struct sdma_csr {
0374     u8  res0[24];
0375     u8  sdma_sdsr;
0376     u8  res1[3];
0377     u8  sdma_sdmr;
0378     u8  res2[3];
0379     u8  sdma_idsr1;
0380     u8  res3[3];
0381     u8  sdma_idmr1;
0382     u8  res4[3];
0383     u8  sdma_idsr2;
0384     u8  res5[3];
0385     u8  sdma_idmr2;
0386     u8  res6[3];
0387     u8  sdma_idsr3;
0388     u8  res7[3];
0389     u8  sdma_idmr3;
0390     u8  res8[3];
0391     u8  sdma_idsr4;
0392     u8  res9[3];
0393     u8  sdma_idmr4;
0394     u8  res10[707];
0395 } sdma_cpm2_t;
0396
0397 /* Fast controllers
0398 */
0399 typedef struct fcc {
0400     u32 fcc_gfmr;
0401     u32 fcc_fpsmr;
0402     u16 fcc_ftodr;
0403     u8  res1[2];
0404     u16 fcc_fdsr;
0405     u8  res2[2];
0406     u16 fcc_fcce;
0407     u8  res3[2];
0408     u16 fcc_fccm;
0409     u8  res4[2];
0410     u8  fcc_fccs;
0411     u8  res5[3];
0412     u8  fcc_ftirr_phy[4];
0413 } fcc_t;
0414
0415 /* Fast controllers continued
0416  */
0417 typedef struct fcc_c {
0418     u32 fcc_firper;
0419     u32 fcc_firer;
0420     u32 fcc_firsr_hi;
0421     u32 fcc_firsr_lo;
0422     u8  fcc_gfemr;
0423     u8  res1[15];
0424 } fcc_c_t;
0425
0426 /* TC Layer
0427  */
0428 typedef struct tclayer {
0429     u16 tc_tcmode;
0430     u16 tc_cdsmr;
0431     u16 tc_tcer;
0432     u16 tc_rcc;
0433     u16 tc_tcmr;
0434     u16 tc_fcc;
0435     u16 tc_ccc;
0436     u16 tc_icc;
0437     u16 tc_tcc;
0438     u16 tc_ecc;
0439     u8  res1[12];
0440 } tclayer_t;
0441
0442
0443 /* I2C
0444 */
0445 typedef struct i2c {
0446     u8  i2c_i2mod;
0447     u8  res1[3];
0448     u8  i2c_i2add;
0449     u8  res2[3];
0450     u8  i2c_i2brg;
0451     u8  res3[3];
0452     u8  i2c_i2com;
0453     u8  res4[3];
0454     u8  i2c_i2cer;
0455     u8  res5[3];
0456     u8  i2c_i2cmr;
0457     u8  res6[331];
0458 } i2c_cpm2_t;
0459
0460 typedef struct scc {        /* Serial communication channels */
0461     u32 scc_gsmrl;
0462     u32 scc_gsmrh;
0463     u16 scc_psmr;
0464     u8  res1[2];
0465     u16 scc_todr;
0466     u16 scc_dsr;
0467     u16 scc_scce;
0468     u8  res2[2];
0469     u16 scc_sccm;
0470     u8  res3;
0471     u8  scc_sccs;
0472     u8  res4[8];
0473 } scc_t;
0474
0475 typedef struct smc {        /* Serial management channels */
0476     u8  res1[2];
0477     u16 smc_smcmr;
0478     u8  res2[2];
0479     u8  smc_smce;
0480     u8  res3[3];
0481     u8  smc_smcm;
0482     u8  res4[5];
0483 } smc_t;
0484
0485 /* Serial Peripheral Interface.
0486 */
0487 typedef struct spi_ctrl {
0488     u16 spi_spmode;
0489     u8  res1[4];
0490     u8  spi_spie;
0491     u8  res2[3];
0492     u8  spi_spim;
0493     u8  res3[2];
0494     u8  spi_spcom;
0495     u8  res4[82];
0496 } spictl_cpm2_t;
0497
0498 /* CPM Mux.
0499 */
0500 typedef struct cpmux {
0501     u8  cmx_si1cr;
0502     u8  res1;
0503     u8  cmx_si2cr;
0504     u8  res2;
0505     u32 cmx_fcr;
0506     u32 cmx_scr;
0507     u8  cmx_smr;
0508     u8  res3;
0509     u16 cmx_uar;
0510     u8  res4[16];
0511 } cpmux_t;
0512
0513 /* SIRAM control
0514 */
0515 typedef struct siram {
0516     u16 si_amr;
0517     u16 si_bmr;
0518     u16 si_cmr;
0519     u16 si_dmr;
0520     u8  si_gmr;
0521     u8  res1;
0522     u8  si_cmdr;
0523     u8  res2;
0524     u8  si_str;
0525     u8  res3;
0526     u16 si_rsr;
0527 } siramctl_t;
0528
0529 typedef struct mcc {
0530     u16 mcc_mcce;
0531     u8  res1[2];
0532     u16 mcc_mccm;
0533     u8  res2[2];
0534     u8  mcc_mccf;
0535     u8  res3[7];
0536 } mcc_t;
0537
0538 typedef struct comm_proc {
0539     u32 cp_cpcr;
0540     u32 cp_rccr;
0541     u8  res1[14];
0542     u16 cp_rter;
0543     u8  res2[2];
0544     u16 cp_rtmr;
0545     u16 cp_rtscr;
0546     u8  res3[2];
0547     u32 cp_rtsr;
0548     u8  res4[12];
0549 } cpm_cpm2_t;
0550
0551 /* USB Controller.
0552 */
0553 typedef struct cpm_usb_ctlr {
0554     u8  usb_usmod;
0555     u8  usb_usadr;
0556     u8  usb_uscom;
0557     u8  res1[1];
0558     __be16  usb_usep[4];
0559     u8  res2[4];
0560     __be16  usb_usber;
0561     u8  res3[2];
0562     __be16  usb_usbmr;
0563     u8  usb_usbs;
0564     u8  res4[7];
0565 } usb_cpm2_t;
0566
0567 /* ...and the whole thing wrapped up....
0568 */
0569
0570 typedef struct immap {
0571     /* Some references are into the unique and known dpram spaces,
0572      * others are from the generic base.
0573      */
0574 #define im_dprambase    im_dpram1
0575     u8      im_dpram1[16*1024];
0576     u8      res1[16*1024];
0577     u8      im_dpram2[4*1024];
0578     u8      res2[8*1024];
0579     u8      im_dpram3[4*1024];
0580     u8      res3[16*1024];
0581
0582     sysconf_cpm2_t  im_siu_conf;    /* SIU Configuration */
0583     memctl_cpm2_t   im_memctl;  /* Memory Controller */
0584     sit_cpm2_t  im_sit;     /* System Integration Timers */
0585     pci_cpm2_t  im_pci;     /* PCI Controller */
0586     intctl_cpm2_t   im_intctl;  /* Interrupt Controller */
0587     car_cpm2_t  im_clkrst;  /* Clocks and reset */
0588     iop_cpm2_t  im_ioport;  /* IO Port control/status */
0589     cpmtimer_cpm2_t im_cpmtimer;    /* CPM timers */
0590     sdma_cpm2_t im_sdma;    /* SDMA control/status */
0591
0592     fcc_t       im_fcc[3];  /* Three FCCs */
0593     u8      res4z[32];
0594     fcc_c_t     im_fcc_c[3];    /* Continued FCCs */
0595
0596     u8      res4[32];
0597
0598     tclayer_t   im_tclayer[8];  /* Eight TCLayers */
0599     u16     tc_tcgsr;
0600     u16     tc_tcger;
0601
0602     /* First set of baud rate generators.
0603     */
0604     u8      res[236];
0605     u32     im_brgc5;
0606     u32     im_brgc6;
0607     u32     im_brgc7;
0608     u32     im_brgc8;
0609
0610     u8      res5[608];
0611
0612     i2c_cpm2_t  im_i2c;     /* I2C control/status */
0613     cpm_cpm2_t  im_cpm;     /* Communication processor */
0614
0615     /* Second set of baud rate generators.
0616     */
0617     u32     im_brgc1;
0618     u32     im_brgc2;
0619     u32     im_brgc3;
0620     u32     im_brgc4;
0621
0622     scc_t       im_scc[4];  /* Four SCCs */
0623     smc_t       im_smc[2];  /* Couple of SMCs */
0624     spictl_cpm2_t   im_spi;     /* A SPI */
0625     cpmux_t     im_cpmux;   /* CPM clock route mux */
0626     siramctl_t  im_siramctl1;   /* First SI RAM Control */
0627     mcc_t       im_mcc1;    /* First MCC */
0628     siramctl_t  im_siramctl2;   /* Second SI RAM Control */
0629     mcc_t       im_mcc2;    /* Second MCC */
0630     usb_cpm2_t  im_usb;     /* USB Controller */
0631
0632     u8      res6[1153];
0633
0634     u16     im_si1txram[256];
0635     u8      res7[512];
0636     u16     im_si1rxram[256];
0637     u8      res8[512];
0638     u16     im_si2txram[256];
0639     u8      res9[512];
0640     u16     im_si2rxram[256];
0641     u8      res10[512];
0642     u8      res11[4096];
0643 } cpm2_map_t;
0644
0645 extern cpm2_map_t __iomem *cpm2_immr;
0646
0647 #endif /* __IMMAP_CPM2__ */
0648 #endif /* __KERNEL__ */