include/asm/icswx.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * ICSWX api
0004  *
0005  * Copyright (C) 2015 IBM Corp.
0006  *
0007  * This provides the Initiate Coprocessor Store Word Indexed (ICSWX)
0008  * instruction.  This instruction is used to communicate with PowerPC
0009  * coprocessors.  This also provides definitions of the structures used
0010  * to communicate with the coprocessor.
0011  *
0012  * The RFC02130: Coprocessor Architecture document is the reference for
0013  * everything in this file unless otherwise noted.
0014  */
0015 #ifndef _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
0016 #define _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_
0017
0018 #include <asm/ppc-opcode.h> /* for PPC_ICSWX */
0019
0020 /* Chapter 6.5.8 Coprocessor-Completion Block (CCB) */
0021
0022 #define CCB_VALUE       (0x3fffffffffffffff)
0023 #define CCB_ADDRESS     (0xfffffffffffffff8)
0024 #define CCB_CM          (0x0000000000000007)
0025 #define CCB_CM0         (0x0000000000000004)
0026 #define CCB_CM12        (0x0000000000000003)
0027
0028 #define CCB_CM0_ALL_COMPLETIONS (0x0)
0029 #define CCB_CM0_LAST_IN_CHAIN   (0x4)
0030 #define CCB_CM12_STORE      (0x0)
0031 #define CCB_CM12_INTERRUPT  (0x1)
0032
0033 #define CCB_SIZE        (0x10)
0034 #define CCB_ALIGN       CCB_SIZE
0035
0036 struct coprocessor_completion_block {
0037     __be64 value;
0038     __be64 address;
0039 } __packed __aligned(CCB_ALIGN);
0040
0041
0042 /* Chapter 6.5.7 Coprocessor-Status Block (CSB) */
0043
0044 #define CSB_V           (0x80)
0045 #define CSB_F           (0x04)
0046 #define CSB_CH          (0x03)
0047 #define CSB_CE_INCOMPLETE   (0x80)
0048 #define CSB_CE_TERMINATION  (0x40)
0049 #define CSB_CE_TPBC     (0x20)
0050
0051 #define CSB_CC_SUCCESS      (0)
0052 #define CSB_CC_INVALID_ALIGN    (1)
0053 #define CSB_CC_OPERAND_OVERLAP  (2)
0054 #define CSB_CC_DATA_LENGTH  (3)
0055 #define CSB_CC_TRANSLATION  (5)
0056 #define CSB_CC_PROTECTION   (6)
0057 #define CSB_CC_RD_EXTERNAL  (7)
0058 #define CSB_CC_INVALID_OPERAND  (8)
0059 #define CSB_CC_PRIVILEGE    (9)
0060 #define CSB_CC_INTERNAL     (10)
0061 #define CSB_CC_WR_EXTERNAL  (12)
0062 #define CSB_CC_NOSPC        (13)
0063 #define CSB_CC_EXCESSIVE_DDE    (14)
0064 #define CSB_CC_WR_TRANSLATION   (15)
0065 #define CSB_CC_WR_PROTECTION    (16)
0066 #define CSB_CC_UNKNOWN_CODE (17)
0067 #define CSB_CC_ABORT        (18)
0068 #define CSB_CC_EXCEED_BYTE_COUNT    (19)    /* P9 or later */
0069 #define CSB_CC_TRANSPORT    (20)
0070 #define CSB_CC_INVALID_CRB  (21)    /* P9 or later */
0071 #define CSB_CC_INVALID_DDE  (30)    /* P9 or later */
0072 #define CSB_CC_SEGMENTED_DDL    (31)
0073 #define CSB_CC_PROGRESS_POINT   (32)
0074 #define CSB_CC_DDE_OVERFLOW (33)
0075 #define CSB_CC_SESSION      (34)
0076 #define CSB_CC_PROVISION    (36)
0077 #define CSB_CC_CHAIN        (37)
0078 #define CSB_CC_SEQUENCE     (38)
0079 #define CSB_CC_HW       (39)
0080 /* P9 DD2 NX Workbook 3.2 (Table 4-36): Address translation fault */
0081 #define CSB_CC_FAULT_ADDRESS    (250)
0082
0083 #define CSB_SIZE        (0x10)
0084 #define CSB_ALIGN       CSB_SIZE
0085
0086 struct coprocessor_status_block {
0087     u8 flags;
0088     u8 cs;
0089     u8 cc;
0090     u8 ce;
0091     __be32 count;
0092     __be64 address;
0093 } __packed __aligned(CSB_ALIGN);
0094
0095
0096 /* Chapter 6.5.10 Data-Descriptor List (DDL)
0097  * each list contains one or more Data-Descriptor Entries (DDE)
0098  */
0099
0100 #define DDE_P           (0x8000)
0101
0102 #define DDE_SIZE        (0x10)
0103 #define DDE_ALIGN       DDE_SIZE
0104
0105 struct data_descriptor_entry {
0106     __be16 flags;
0107     u8 count;
0108     u8 index;
0109     __be32 length;
0110     __be64 address;
0111 } __packed __aligned(DDE_ALIGN);
0112
0113 /* 4.3.2 NX-stamped Fault CRB */
0114
0115 #define NX_STAMP_ALIGN          (0x10)
0116
0117 struct nx_fault_stamp {
0118     __be64 fault_storage_addr;
0119     __be16 reserved;
0120     __u8   flags;
0121     __u8   fault_status;
0122     __be32 pswid;
0123 } __packed __aligned(NX_STAMP_ALIGN);
0124
0125 /* Chapter 6.5.2 Coprocessor-Request Block (CRB) */
0126
0127 #define CRB_SIZE        (0x80)
0128 #define CRB_ALIGN       (0x100) /* Errata: requires 256 alignment */
0129
0130 /* Coprocessor Status Block field
0131  *   ADDRESS    address of CSB
0132  *   C      CCB is valid
0133  *   AT     0 = addrs are virtual, 1 = addrs are phys
0134  *   M      enable perf monitor
0135  */
0136 #define CRB_CSB_ADDRESS     (0xfffffffffffffff0)
0137 #define CRB_CSB_C       (0x0000000000000008)
0138 #define CRB_CSB_AT      (0x0000000000000002)
0139 #define CRB_CSB_M       (0x0000000000000001)
0140
0141 struct coprocessor_request_block {
0142     __be32 ccw;
0143     __be32 flags;
0144     __be64 csb_addr;
0145
0146     struct data_descriptor_entry source;
0147     struct data_descriptor_entry target;
0148
0149     struct coprocessor_completion_block ccb;
0150
0151     union {
0152         struct nx_fault_stamp nx;
0153         u8 reserved[16];
0154     } stamp;
0155
0156     u8 reserved[32];
0157
0158     struct coprocessor_status_block csb;
0159 } __aligned(128);
0160
0161 /* RFC02167 Initiate Coprocessor Instructions document
0162  * Chapter 8.2.1.1.1 RS
0163  * Chapter 8.2.3 Coprocessor Directive
0164  * Chapter 8.2.4 Execution
0165  *
0166  * The CCW must be converted to BE before passing to icswx()
0167  */
0168
0169 #define CCW_PS          (0xff000000)
0170 #define CCW_CT          (0x00ff0000)
0171 #define CCW_CD          (0x0000ffff)
0172 #define CCW_CL          (0x0000c000)
0173
0174
0175 /* RFC02167 Initiate Coprocessor Instructions document
0176  * Chapter 8.2.1 Initiate Coprocessor Store Word Indexed (ICSWX)
0177  * Chapter 8.2.4.1 Condition Register 0
0178  */
0179
0180 #define ICSWX_INITIATED     (0x8)
0181 #define ICSWX_BUSY      (0x4)
0182 #define ICSWX_REJECTED      (0x2)
0183 #define ICSWX_XERS0     (0x1)   /* undefined or set from XERSO. */
0184
0185 static inline int icswx(__be32 ccw, struct coprocessor_request_block *crb)
0186 {
0187     __be64 ccw_reg = ccw;
0188     u32 cr;
0189
0190     /* NB: the same structures are used by VAS-NX */
0191     BUILD_BUG_ON(sizeof(*crb) != 128);
0192
0193     __asm__ __volatile__(
0194     PPC_ICSWX(%1,0,%2) "\n"
0195     "mfcr %0\n"
0196     : "=r" (cr)
0197     : "r" (ccw_reg), "r" (crb)
0198     : "cr0", "memory");
0199
0200     return (int)((cr >> 28) & 0xf);
0201 }
0202
0203
0204 #endif /* _ARCH_POWERPC_INCLUDE_ASM_ICSWX_H_ */