include/asm/hydra.h

0001 /*
0002  *  include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
0003  *
0004  *  Copyright (C) 1997 Geert Uytterhoeven
0005  *
0006  *  This file is based on the following documentation:
0007  *
0008  *  Macintosh Technology in the Common Hardware Reference Platform
0009  *  Apple Computer, Inc.
0010  *
0011  *  © Copyright 1995 Apple Computer, Inc. All rights reserved.
0012  *
0013  *  It's available online from https://www.cpu.lu/~mlan/ftp/MacTech.pdf
0014  *  You can obtain paper copies of this book from computer bookstores or by
0015  *  writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
0016  *  Francisco, CA 94104. Reference ISBN 1-55860-393-X.
0017  *
0018  *  This file is subject to the terms and conditions of the GNU General Public
0019  *  License.  See the file COPYING in the main directory of this archive
0020  *  for more details.
0021  */
0022
0023 #ifndef _ASMPPC_HYDRA_H
0024 #define _ASMPPC_HYDRA_H
0025
0026 #ifdef __KERNEL__
0027
0028 struct Hydra {
0029     /* DBDMA Controller Register Space */
0030     char Pad1[0x30];
0031     u_int CachePD;
0032     u_int IDs;
0033     u_int Feature_Control;
0034     char Pad2[0x7fc4];
0035     /* DBDMA Channel Register Space */
0036     char SCSI_DMA[0x100];
0037     char Pad3[0x300];
0038     char SCCA_Tx_DMA[0x100];
0039     char SCCA_Rx_DMA[0x100];
0040     char SCCB_Tx_DMA[0x100];
0041     char SCCB_Rx_DMA[0x100];
0042     char Pad4[0x7800];
0043     /* Device Register Space */
0044     char SCSI[0x1000];
0045     char ADB[0x1000];
0046     char SCC_Legacy[0x1000];
0047     char SCC[0x1000];
0048     char Pad9[0x2000];
0049     char VIA[0x2000];
0050     char Pad10[0x28000];
0051     char OpenPIC[0x40000];
0052 };
0053
0054 extern volatile struct Hydra __iomem *Hydra;
0055
0056
0057     /*
0058      *  Feature Control Register
0059      */
0060
0061 #define HYDRA_FC_SCC_CELL_EN    0x00000001  /* Enable SCC Clock */
0062 #define HYDRA_FC_SCSI_CELL_EN   0x00000002  /* Enable SCSI Clock */
0063 #define HYDRA_FC_SCCA_ENABLE    0x00000004  /* Enable SCC A Lines */
0064 #define HYDRA_FC_SCCB_ENABLE    0x00000008  /* Enable SCC B Lines */
0065 #define HYDRA_FC_ARB_BYPASS 0x00000010  /* Bypass Internal Arbiter */
0066 #define HYDRA_FC_RESET_SCC  0x00000020  /* Reset SCC */
0067 #define HYDRA_FC_MPIC_ENABLE    0x00000040  /* Enable OpenPIC */
0068 #define HYDRA_FC_SLOW_SCC_PCLK  0x00000080  /* 1=15.6672, 0=25 MHz */
0069 #define HYDRA_FC_MPIC_IS_MASTER 0x00000100  /* OpenPIC Master Mode */
0070
0071
0072     /*
0073      *  OpenPIC Interrupt Sources
0074      */
0075
0076 #define HYDRA_INT_SIO       0
0077 #define HYDRA_INT_SCSI_DMA  1
0078 #define HYDRA_INT_SCCA_TX_DMA   2
0079 #define HYDRA_INT_SCCA_RX_DMA   3
0080 #define HYDRA_INT_SCCB_TX_DMA   4
0081 #define HYDRA_INT_SCCB_RX_DMA   5
0082 #define HYDRA_INT_SCSI      6
0083 #define HYDRA_INT_SCCA      7
0084 #define HYDRA_INT_SCCB      8
0085 #define HYDRA_INT_VIA       9
0086 #define HYDRA_INT_ADB       10
0087 #define HYDRA_INT_ADB_NMI   11
0088 #define HYDRA_INT_EXT1      12  /* PCI IRQW */
0089 #define HYDRA_INT_EXT2      13  /* PCI IRQX */
0090 #define HYDRA_INT_EXT3      14  /* PCI IRQY */
0091 #define HYDRA_INT_EXT4      15  /* PCI IRQZ */
0092 #define HYDRA_INT_EXT5      16  /* IDE Primary/Secondary */
0093 #define HYDRA_INT_EXT6      17  /* IDE Secondary */
0094 #define HYDRA_INT_EXT7      18  /* Power Off Request */
0095 #define HYDRA_INT_SPARE     19
0096
0097 #endif /* __KERNEL__ */
0098
0099 #endif /* _ASMPPC_HYDRA_H */