include/asm/heathrow.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_HEATHROW_H
0003 #define _ASM_POWERPC_HEATHROW_H
0004 #ifdef __KERNEL__
0005 /*
0006  * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
0007  *
0008  * Grabbed from Open Firmware definitions on a PowerBook G3 Series
0009  *
0010  * Copyright (C) 1997 Paul Mackerras.
0011  */
0012
0013 /* Front light color on Yikes/B&W G3. 32 bits */
0014 #define HEATHROW_FRONT_LIGHT        0x32 /* (set to 0 or 0xffffffff) */
0015
0016 /* Brightness/contrast (gossamer iMac ?). 8 bits */
0017 #define HEATHROW_BRIGHTNESS_CNTL    0x32
0018 #define HEATHROW_CONTRAST_CNTL      0x33
0019
0020 /* offset from ohare base for feature control register */
0021 #define HEATHROW_MBCR           0x34    /* Media bay control */
0022 #define HEATHROW_FCR            0x38    /* Feature control */
0023 #define HEATHROW_AUX_CNTL_REG       0x3c    /* Aux control */
0024
0025 /*
0026  * Bits in feature control register.
0027  * Bits postfixed with a _N are in inverse logic
0028  */
0029 #define HRW_SCC_TRANS_EN_N  0x00000001  /* Also controls modem power */
0030 #define HRW_BAY_POWER_N     0x00000002
0031 #define HRW_BAY_PCI_ENABLE  0x00000004
0032 #define HRW_BAY_IDE_ENABLE  0x00000008
0033 #define HRW_BAY_FLOPPY_ENABLE   0x00000010
0034 #define HRW_IDE0_ENABLE     0x00000020
0035 #define HRW_IDE0_RESET_N    0x00000040
0036 #define HRW_BAY_DEV_MASK    0x0000001c
0037 #define HRW_BAY_RESET_N     0x00000080
0038 #define HRW_IOBUS_ENABLE    0x00000100  /* Internal IDE ? */
0039 #define HRW_SCC_ENABLE      0x00000200
0040 #define HRW_MESH_ENABLE     0x00000400
0041 #define HRW_SWIM_ENABLE     0x00000800
0042 #define HRW_SOUND_POWER_N   0x00001000
0043 #define HRW_SOUND_CLK_ENABLE    0x00002000
0044 #define HRW_SCCA_IO     0x00004000
0045 #define HRW_SCCB_IO     0x00008000
0046 #define HRW_PORT_OR_DESK_VIA_N  0x00010000  /* This one is 0 on PowerBook */
0047 #define HRW_PWM_MON_ID_N    0x00020000  /* ??? (0) */
0048 #define HRW_HOOK_MB_CNT_N   0x00040000  /* ??? (0) */
0049 #define HRW_SWIM_CLONE_FLOPPY   0x00080000  /* ??? (0) */
0050 #define HRW_AUD_RUN22       0x00100000  /* ??? (1) */
0051 #define HRW_SCSI_LINK_MODE  0x00200000  /* Read ??? (1) */
0052 #define HRW_ARB_BYPASS      0x00400000  /* Disable internal PCI arbitrer */
0053 #define HRW_IDE1_RESET_N    0x00800000  /* Media bay */
0054 #define HRW_SLOW_SCC_PCLK   0x01000000  /* ??? (0) */
0055 #define HRW_RESET_SCC       0x02000000
0056 #define HRW_MFDC_CELL_ENABLE    0x04000000  /* ??? (0) */
0057 #define HRW_USE_MFDC        0x08000000  /* ??? (0) */
0058 #define HRW_BMAC_IO_ENABLE  0x60000000  /* two bits, not documented in OF */
0059 #define HRW_BMAC_RESET      0x80000000  /* not documented in OF */
0060
0061 /* We OR those features at boot on desktop G3s */
0062 #define HRW_DEFAULTS        (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
0063
0064 /* Looks like Heathrow has some sort of GPIOs as well... */
0065 #define HRW_GPIO_MODEM_RESET    0x6d
0066
0067 #endif /* __KERNEL__ */
0068 #endif /* _ASM_POWERPC_HEATHROW_H */