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0007 #ifndef __PPC_FSL_PM_H
0008 #define __PPC_FSL_PM_H
0009
0010 #define E500_PM_PH10 1
0011 #define E500_PM_PH15 2
0012 #define E500_PM_PH20 3
0013 #define E500_PM_PH30 4
0014 #define E500_PM_DOZE E500_PM_PH10
0015 #define E500_PM_NAP E500_PM_PH15
0016
0017 #define PLAT_PM_SLEEP 20
0018 #define PLAT_PM_LPM20 30
0019
0020 #define FSL_PM_SLEEP (1 << 0)
0021 #define FSL_PM_DEEP_SLEEP (1 << 1)
0022
0023 struct fsl_pm_ops {
0024
0025 void (*irq_mask)(int cpu);
0026
0027
0028 void (*irq_unmask)(int cpu);
0029 void (*cpu_enter_state)(int cpu, int state);
0030 void (*cpu_exit_state)(int cpu, int state);
0031 void (*cpu_up_prepare)(int cpu);
0032 void (*cpu_die)(int cpu);
0033 int (*plat_enter_sleep)(void);
0034 void (*freeze_time_base)(bool freeze);
0035
0036
0037 void (*set_ip_power)(bool enable, u32 mask);
0038
0039
0040 unsigned int (*get_pm_modes)(void);
0041 };
0042
0043 extern const struct fsl_pm_ops *qoriq_pm_ops;
0044
0045 int __init fsl_rcpm_init(void);
0046
0047 #endif