include/asm/fsl_lbc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Freescale Local Bus Controller
0003  *
0004  * Copyright © 2006-2007, 2010 Freescale Semiconductor
0005  *
0006  * Authors: Nick Spence <nick.spence@freescale.com>,
0007  *          Scott Wood <scottwood@freescale.com>
0008  *          Jack Lan <jack.lan@freescale.com>
0009  */
0010
0011 #ifndef __ASM_FSL_LBC_H
0012 #define __ASM_FSL_LBC_H
0013
0014 #include <linux/compiler.h>
0015 #include <linux/types.h>
0016 #include <linux/io.h>
0017 #include <linux/device.h>
0018 #include <linux/spinlock.h>
0019
0020 struct fsl_lbc_bank {
0021     __be32 br;             /**< Base Register  */
0022 #define BR_BA           0xFFFF8000
0023 #define BR_BA_SHIFT             15
0024 #define BR_PS           0x00001800
0025 #define BR_PS_SHIFT             11
0026 #define BR_PS_8         0x00000800  /* Port Size 8 bit */
0027 #define BR_PS_16        0x00001000  /* Port Size 16 bit */
0028 #define BR_PS_32        0x00001800  /* Port Size 32 bit */
0029 #define BR_DECC         0x00000600
0030 #define BR_DECC_SHIFT            9
0031 #define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
0032 #define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
0033 #define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
0034 #define BR_WP           0x00000100
0035 #define BR_WP_SHIFT              8
0036 #define BR_MSEL         0x000000E0
0037 #define BR_MSEL_SHIFT            5
0038 #define BR_MS_GPCM      0x00000000  /* GPCM */
0039 #define BR_MS_FCM       0x00000020  /* FCM */
0040 #define BR_MS_SDRAM     0x00000060  /* SDRAM */
0041 #define BR_MS_UPMA      0x00000080  /* UPMA */
0042 #define BR_MS_UPMB      0x000000A0  /* UPMB */
0043 #define BR_MS_UPMC      0x000000C0  /* UPMC */
0044 #define BR_V            0x00000001
0045 #define BR_V_SHIFT               0
0046 #define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
0047
0048     __be32 or;             /**< Base Register  */
0049 #define OR0 0x5004
0050 #define OR1 0x500C
0051 #define OR2 0x5014
0052 #define OR3 0x501C
0053 #define OR4 0x5024
0054 #define OR5 0x502C
0055 #define OR6 0x5034
0056 #define OR7 0x503C
0057
0058 #define OR_FCM_AM               0xFFFF8000
0059 #define OR_FCM_AM_SHIFT                 15
0060 #define OR_FCM_BCTLD            0x00001000
0061 #define OR_FCM_BCTLD_SHIFT              12
0062 #define OR_FCM_PGS              0x00000400
0063 #define OR_FCM_PGS_SHIFT                10
0064 #define OR_FCM_CSCT             0x00000200
0065 #define OR_FCM_CSCT_SHIFT                9
0066 #define OR_FCM_CST              0x00000100
0067 #define OR_FCM_CST_SHIFT                 8
0068 #define OR_FCM_CHT              0x00000080
0069 #define OR_FCM_CHT_SHIFT                 7
0070 #define OR_FCM_SCY              0x00000070
0071 #define OR_FCM_SCY_SHIFT                 4
0072 #define OR_FCM_SCY_1            0x00000010
0073 #define OR_FCM_SCY_2            0x00000020
0074 #define OR_FCM_SCY_3            0x00000030
0075 #define OR_FCM_SCY_4            0x00000040
0076 #define OR_FCM_SCY_5            0x00000050
0077 #define OR_FCM_SCY_6            0x00000060
0078 #define OR_FCM_SCY_7            0x00000070
0079 #define OR_FCM_RST              0x00000008
0080 #define OR_FCM_RST_SHIFT                 3
0081 #define OR_FCM_TRLX             0x00000004
0082 #define OR_FCM_TRLX_SHIFT                2
0083 #define OR_FCM_EHTR             0x00000002
0084 #define OR_FCM_EHTR_SHIFT                1
0085
0086 #define OR_GPCM_AM      0xFFFF8000
0087 #define OR_GPCM_AM_SHIFT        15
0088 };
0089
0090 struct fsl_lbc_regs {
0091     struct fsl_lbc_bank bank[12];
0092     u8 res0[0x8];
0093     __be32 mar;             /**< UPM Address Register */
0094     u8 res1[0x4];
0095     __be32 mamr;            /**< UPMA Mode Register */
0096 #define MxMR_OP_NO  (0 << 28) /**< normal operation */
0097 #define MxMR_OP_WA  (1 << 28) /**< write array */
0098 #define MxMR_OP_RA  (2 << 28) /**< read array */
0099 #define MxMR_OP_RP  (3 << 28) /**< run pattern */
0100 #define MxMR_MAD    0x3f      /**< machine address */
0101     __be32 mbmr;            /**< UPMB Mode Register */
0102     __be32 mcmr;            /**< UPMC Mode Register */
0103     u8 res2[0x8];
0104     __be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
0105     __be32 mdr;             /**< UPM Data Register */
0106     u8 res3[0x4];
0107     __be32 lsor;            /**< Special Operation Initiation Register */
0108     __be32 lsdmr;           /**< SDRAM Mode Register */
0109     u8 res4[0x8];
0110     __be32 lurt;            /**< UPM Refresh Timer */
0111     __be32 lsrt;            /**< SDRAM Refresh Timer */
0112     u8 res5[0x8];
0113     __be32 ltesr;           /**< Transfer Error Status Register */
0114 #define LTESR_BM   0x80000000
0115 #define LTESR_FCT  0x40000000
0116 #define LTESR_PAR  0x20000000
0117 #define LTESR_WP   0x04000000
0118 #define LTESR_ATMW 0x00800000
0119 #define LTESR_ATMR 0x00400000
0120 #define LTESR_CS   0x00080000
0121 #define LTESR_UPM  0x00000002
0122 #define LTESR_CC   0x00000001
0123 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
0124 #define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
0125              | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
0126              | LTESR_CC)
0127 #define LTESR_CLEAR 0xFFFFFFFF
0128 #define LTECCR_CLEAR    0xFFFFFFFF
0129 #define LTESR_STATUS    LTESR_MASK
0130 #define LTEIR_ENABLE    LTESR_MASK
0131 #define LTEDR_ENABLE    0x00000000
0132     __be32 ltedr;           /**< Transfer Error Disable Register */
0133     __be32 lteir;           /**< Transfer Error Interrupt Register */
0134     __be32 lteatr;          /**< Transfer Error Attributes Register */
0135     __be32 ltear;           /**< Transfer Error Address Register */
0136     __be32 lteccr;          /**< Transfer Error ECC Register */
0137     u8 res6[0x8];
0138     __be32 lbcr;            /**< Configuration Register */
0139 #define LBCR_LDIS  0x80000000
0140 #define LBCR_LDIS_SHIFT    31
0141 #define LBCR_BCTLC 0x00C00000
0142 #define LBCR_BCTLC_SHIFT   22
0143 #define LBCR_AHD   0x00200000
0144 #define LBCR_LPBSE 0x00020000
0145 #define LBCR_LPBSE_SHIFT   17
0146 #define LBCR_EPAR  0x00010000
0147 #define LBCR_EPAR_SHIFT    16
0148 #define LBCR_BMT   0x0000FF00
0149 #define LBCR_BMT_SHIFT      8
0150 #define LBCR_BMTPS 0x0000000F
0151 #define LBCR_BMTPS_SHIFT    0
0152 #define LBCR_INIT  0x00040000
0153     __be32 lcrr;            /**< Clock Ratio Register */
0154 #define LCRR_DBYP    0x80000000
0155 #define LCRR_DBYP_SHIFT      31
0156 #define LCRR_BUFCMDC 0x30000000
0157 #define LCRR_BUFCMDC_SHIFT   28
0158 #define LCRR_ECL     0x03000000
0159 #define LCRR_ECL_SHIFT       24
0160 #define LCRR_EADC    0x00030000
0161 #define LCRR_EADC_SHIFT      16
0162 #define LCRR_CLKDIV  0x0000000F
0163 #define LCRR_CLKDIV_SHIFT     0
0164     u8 res7[0x8];
0165     __be32 fmr;             /**< Flash Mode Register */
0166 #define FMR_CWTO     0x0000F000
0167 #define FMR_CWTO_SHIFT       12
0168 #define FMR_BOOT     0x00000800
0169 #define FMR_ECCM     0x00000100
0170 #define FMR_AL       0x00000030
0171 #define FMR_AL_SHIFT          4
0172 #define FMR_OP       0x00000003
0173 #define FMR_OP_SHIFT          0
0174     __be32 fir;             /**< Flash Instruction Register */
0175 #define FIR_OP0      0xF0000000
0176 #define FIR_OP0_SHIFT        28
0177 #define FIR_OP1      0x0F000000
0178 #define FIR_OP1_SHIFT        24
0179 #define FIR_OP2      0x00F00000
0180 #define FIR_OP2_SHIFT        20
0181 #define FIR_OP3      0x000F0000
0182 #define FIR_OP3_SHIFT        16
0183 #define FIR_OP4      0x0000F000
0184 #define FIR_OP4_SHIFT        12
0185 #define FIR_OP5      0x00000F00
0186 #define FIR_OP5_SHIFT         8
0187 #define FIR_OP6      0x000000F0
0188 #define FIR_OP6_SHIFT         4
0189 #define FIR_OP7      0x0000000F
0190 #define FIR_OP7_SHIFT         0
0191 #define FIR_OP_NOP   0x0    /* No operation and end of sequence */
0192 #define FIR_OP_CA    0x1        /* Issue current column address */
0193 #define FIR_OP_PA    0x2        /* Issue current block+page address */
0194 #define FIR_OP_UA    0x3        /* Issue user defined address */
0195 #define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
0196 #define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
0197 #define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
0198 #define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
0199 #define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
0200 #define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
0201 #define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
0202 #define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
0203 #define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
0204 #define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
0205 #define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
0206 #define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
0207     __be32 fcr;             /**< Flash Command Register */
0208 #define FCR_CMD0     0xFF000000
0209 #define FCR_CMD0_SHIFT       24
0210 #define FCR_CMD1     0x00FF0000
0211 #define FCR_CMD1_SHIFT       16
0212 #define FCR_CMD2     0x0000FF00
0213 #define FCR_CMD2_SHIFT        8
0214 #define FCR_CMD3     0x000000FF
0215 #define FCR_CMD3_SHIFT        0
0216     __be32 fbar;            /**< Flash Block Address Register */
0217 #define FBAR_BLK     0x00FFFFFF
0218     __be32 fpar;            /**< Flash Page Address Register */
0219 #define FPAR_SP_PI   0x00007C00
0220 #define FPAR_SP_PI_SHIFT     10
0221 #define FPAR_SP_MS   0x00000200
0222 #define FPAR_SP_CI   0x000001FF
0223 #define FPAR_SP_CI_SHIFT      0
0224 #define FPAR_LP_PI   0x0003F000
0225 #define FPAR_LP_PI_SHIFT     12
0226 #define FPAR_LP_MS   0x00000800
0227 #define FPAR_LP_CI   0x000007FF
0228 #define FPAR_LP_CI_SHIFT      0
0229     __be32 fbcr;            /**< Flash Byte Count Register */
0230 #define FBCR_BC      0x00000FFF
0231 };
0232
0233 /*
0234  * FSL UPM routines
0235  */
0236 struct fsl_upm {
0237     __be32 __iomem *mxmr;
0238     int width;
0239 };
0240
0241 extern u32 fsl_lbc_addr(phys_addr_t addr_base);
0242 extern int fsl_lbc_find(phys_addr_t addr_base);
0243 extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);
0244
0245 /**
0246  * fsl_upm_start_pattern - start UPM patterns execution
0247  * @upm:    pointer to the fsl_upm structure obtained via fsl_upm_find
0248  * @pat_offset: UPM pattern offset for the command to be executed
0249  *
0250  * This routine programmes UPM so the next memory access that hits an UPM
0251  * will trigger pattern execution, starting at pat_offset.
0252  */
0253 static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
0254 {
0255     clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
0256 }
0257
0258 /**
0259  * fsl_upm_end_pattern - end UPM patterns execution
0260  * @upm:    pointer to the fsl_upm structure obtained via fsl_upm_find
0261  *
0262  * This routine reverts UPM to normal operation mode.
0263  */
0264 static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
0265 {
0266     clrbits32(upm->mxmr, MxMR_OP_RP);
0267
0268     while (in_be32(upm->mxmr) & MxMR_OP_RP)
0269         cpu_relax();
0270 }
0271
0272 /* overview of the fsl lbc controller */
0273
0274 struct fsl_lbc_ctrl {
0275     /* device info */
0276     struct device           *dev;
0277     struct fsl_lbc_regs __iomem *regs;
0278     int             irq[2];
0279     wait_queue_head_t       irq_wait;
0280     spinlock_t          lock;
0281     void                *nand;
0282
0283     /* status read from LTESR by irq handler */
0284     unsigned int            irq_status;
0285
0286 #ifdef CONFIG_SUSPEND
0287     /* save regs when system go to deep-sleep */
0288     struct fsl_lbc_regs     *saved_regs;
0289 #endif
0290 };
0291
0292 extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
0293                    u32 mar);
0294 extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
0295
0296 #endif /* __ASM_FSL_LBC_H */