include/asm/exception-64e.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  Definitions for use by exception code on Book3-E
0004  *
0005  *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
0006  */
0007 #ifndef _ASM_POWERPC_EXCEPTION_64E_H
0008 #define _ASM_POWERPC_EXCEPTION_64E_H
0009
0010 /*
0011  * SPRGs usage an other considerations...
0012  *
0013  * Since TLB miss and other standard exceptions can be interrupted by
0014  * critical exceptions which can themselves be interrupted by machine
0015  * checks, and since the two later can themselves cause a TLB miss when
0016  * hitting the linear mapping for the kernel stacks, we need to be a bit
0017  * creative on how we use SPRGs.
0018  *
0019  * The base idea is that we have one SRPG reserved for critical and one
0020  * for machine check interrupts. Those are used to save a GPR that can
0021  * then be used to get the PACA, and store as much context as we need
0022  * to save in there. That includes saving the SPRGs used by the TLB miss
0023  * handler for linear mapping misses and the associated SRR0/1 due to
0024  * the above re-entrancy issue.
0025  *
0026  * So here's the current usage pattern. It's done regardless of which
0027  * SPRGs are user-readable though, thus we might have to change some of
0028  * this later. In order to do that more easily, we use special constants
0029  * for naming them
0030  *
0031  * WARNING: Some of these SPRGs are user readable. We need to do something
0032  * about it as some point by making sure they can't be used to leak kernel
0033  * critical data
0034  */
0035
0036 #define PACA_EXGDBELL PACA_EXGEN
0037
0038 /* We are out of SPRGs so we save some things in the PACA. The normal
0039  * exception frame is smaller than the CRIT or MC one though
0040  */
0041 #define EX_R1       (0 * 8)
0042 #define EX_CR       (1 * 8)
0043 #define EX_R10      (2 * 8)
0044 #define EX_R11      (3 * 8)
0045 #define EX_R14      (4 * 8)
0046 #define EX_R15      (5 * 8)
0047
0048 /*
0049  * The TLB miss exception uses different slots.
0050  *
0051  * The bolted variant uses only the first six fields,
0052  * which in combination with pgd and kernel_pgd fits in
0053  * one 64-byte cache line.
0054  */
0055
0056 #define EX_TLB_R10  ( 0 * 8)
0057 #define EX_TLB_R11  ( 1 * 8)
0058 #define EX_TLB_R14  ( 2 * 8)
0059 #define EX_TLB_R15  ( 3 * 8)
0060 #define EX_TLB_R16  ( 4 * 8)
0061 #define EX_TLB_CR   ( 5 * 8)
0062 #define EX_TLB_R12  ( 6 * 8)
0063 #define EX_TLB_R13  ( 7 * 8)
0064 #define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */
0065 #define EX_TLB_ESR  ( 9 * 8) /* Level 0 and 2 only */
0066 #define EX_TLB_SRR0 (10 * 8)
0067 #define EX_TLB_SRR1 (11 * 8)
0068 #define EX_TLB_R7   (12 * 8)
0069 #define EX_TLB_SIZE (13 * 8)
0070
0071 #define START_EXCEPTION(label)                      \
0072     .globl exc_##label##_book3e;                    \
0073 exc_##label##_book3e:
0074
0075 /* TLB miss exception prolog
0076  *
0077  * This prolog handles re-entrancy (up to 3 levels supported in the PACA
0078  * though we currently don't test for overflow). It provides you with a
0079  * re-entrancy safe working space of r10...r16 and CR with r12 being used
0080  * as the exception area pointer in the PACA for that level of re-entrancy
0081  * and r13 containing the PACA pointer.
0082  *
0083  * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply
0084  * as-is for instruction exceptions. It's up to the actual exception code
0085  * to save them as well if required.
0086  */
0087 #define TLB_MISS_PROLOG                             \
0088     mtspr   SPRN_SPRG_TLB_SCRATCH,r12;                  \
0089     mfspr   r12,SPRN_SPRG_TLB_EXFRAME;                  \
0090     std r10,EX_TLB_R10(r12);                        \
0091     mfcr    r10;                                \
0092     std r11,EX_TLB_R11(r12);                        \
0093     mfspr   r11,SPRN_SPRG_TLB_SCRATCH;                  \
0094     std r13,EX_TLB_R13(r12);                        \
0095     mfspr   r13,SPRN_SPRG_PACA;                     \
0096     std r14,EX_TLB_R14(r12);                        \
0097     addi    r14,r12,EX_TLB_SIZE;                        \
0098     std r15,EX_TLB_R15(r12);                        \
0099     mfspr   r15,SPRN_SRR1;                          \
0100     std r16,EX_TLB_R16(r12);                        \
0101     mfspr   r16,SPRN_SRR0;                          \
0102     std r10,EX_TLB_CR(r12);                     \
0103     std r11,EX_TLB_R12(r12);                        \
0104     mtspr   SPRN_SPRG_TLB_EXFRAME,r14;                  \
0105     std r15,EX_TLB_SRR1(r12);                       \
0106     std r16,EX_TLB_SRR0(r12);
0107
0108 /* And these are the matching epilogs that restores things
0109  *
0110  * There are 3 epilogs:
0111  *
0112  * - SUCCESS       : Unwinds one level
0113  * - ERROR         : restore from level 0 and reset
0114  * - ERROR_SPECIAL : restore from current level and reset
0115  *
0116  * Normal errors use ERROR, that is, they restore the initial fault context
0117  * and trigger a fault. However, there is a special case for linear mapping
0118  * errors. Those should basically never happen, but if they do happen, we
0119  * want the error to point out the context that did that linear mapping
0120  * fault, not the initial level 0 (basically, we got a bogus PGF or something
0121  * like that). For userland errors on the linear mapping, there is no
0122  * difference since those are always level 0 anyway
0123  */
0124
0125 #define TLB_MISS_RESTORE(freg)                          \
0126     ld  r14,EX_TLB_CR(r12);                     \
0127     ld  r10,EX_TLB_R10(r12);                        \
0128     ld  r15,EX_TLB_SRR0(r12);                       \
0129     ld  r16,EX_TLB_SRR1(r12);                       \
0130     mtspr   SPRN_SPRG_TLB_EXFRAME,freg;                 \
0131     ld  r11,EX_TLB_R11(r12);                        \
0132     mtcr    r14;                                \
0133     ld  r13,EX_TLB_R13(r12);                        \
0134     ld  r14,EX_TLB_R14(r12);                        \
0135     mtspr   SPRN_SRR0,r15;                          \
0136     ld  r15,EX_TLB_R15(r12);                        \
0137     mtspr   SPRN_SRR1,r16;                          \
0138     ld  r16,EX_TLB_R16(r12);                        \
0139     ld  r12,EX_TLB_R12(r12);                        \
0140
0141 #define TLB_MISS_EPILOG_SUCCESS                         \
0142     TLB_MISS_RESTORE(r12)
0143
0144 #define TLB_MISS_EPILOG_ERROR                           \
0145     addi    r12,r13,PACA_EXTLB;                     \
0146     TLB_MISS_RESTORE(r12)
0147
0148 #define TLB_MISS_EPILOG_ERROR_SPECIAL                       \
0149     addi    r11,r13,PACA_EXTLB;                     \
0150     TLB_MISS_RESTORE(r11)
0151
0152 #ifndef __ASSEMBLY__
0153 extern unsigned int interrupt_base_book3e;
0154 #endif
0155
0156 #define SET_IVOR(vector_number, vector_offset)  \
0157     LOAD_REG_ADDR(r3,interrupt_base_book3e);\
0158     ori r3,r3,vector_offset@l;      \
0159     mtspr   SPRN_IVOR##vector_number,r3;
0160 /*
0161  * powerpc relies on return from interrupt/syscall being context synchronising
0162  * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
0163  * synchronisation instructions.
0164  */
0165 #define RFI_TO_KERNEL                           \
0166     rfi
0167
0168 #define RFI_TO_USER                         \
0169     rfi
0170
0171 #endif /* _ASM_POWERPC_EXCEPTION_64E_H */
0172