include/asm/eeh.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
0004  * Copyright 2001-2012 IBM Corporation.
0005  */
0006
0007 #ifndef _POWERPC_EEH_H
0008 #define _POWERPC_EEH_H
0009 #ifdef __KERNEL__
0010
0011 #include <linux/init.h>
0012 #include <linux/list.h>
0013 #include <linux/string.h>
0014 #include <linux/time.h>
0015 #include <linux/atomic.h>
0016
0017 #include <uapi/asm/eeh.h>
0018
0019 struct pci_dev;
0020 struct pci_bus;
0021 struct pci_dn;
0022
0023 #ifdef CONFIG_EEH
0024
0025 /* EEH subsystem flags */
0026 #define EEH_ENABLED     0x01    /* EEH enabled               */
0027 #define EEH_FORCE_DISABLED  0x02    /* EEH disabled              */
0028 #define EEH_PROBE_MODE_DEV  0x04    /* From PCI device           */
0029 #define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree          */
0030 #define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log             */
0031 #define EEH_EARLY_DUMP_LOG  0x40    /* Dump log immediately          */
0032
0033 /*
0034  * Delay for PE reset, all in ms
0035  *
0036  * PCI specification has reset hold time of 100 milliseconds.
0037  * We have 250 milliseconds here. The PCI bus settlement time
0038  * is specified as 1.5 seconds and we have 1.8 seconds.
0039  */
0040 #define EEH_PE_RST_HOLD_TIME        250
0041 #define EEH_PE_RST_SETTLE_TIME      1800
0042
0043 /*
0044  * The struct is used to trace PE related EEH functionality.
0045  * In theory, there will have one instance of the struct to
0046  * be created against particular PE. In nature, PEs correlate
0047  * to each other. the struct has to reflect that hierarchy in
0048  * order to easily pick up those affected PEs when one particular
0049  * PE has EEH errors.
0050  *
0051  * Also, one particular PE might be composed of PCI device, PCI
0052  * bus and its subordinate components. The struct also need ship
0053  * the information. Further more, one particular PE is only meaingful
0054  * in the corresponding PHB. Therefore, the root PEs should be created
0055  * against existing PHBs in on-to-one fashion.
0056  */
0057 #define EEH_PE_INVALID  (1 << 0)    /* Invalid   */
0058 #define EEH_PE_PHB  (1 << 1)    /* PHB PE    */
0059 #define EEH_PE_DEVICE   (1 << 2)    /* Device PE */
0060 #define EEH_PE_BUS  (1 << 3)    /* Bus PE    */
0061 #define EEH_PE_VF   (1 << 4)    /* VF PE     */
0062
0063 #define EEH_PE_ISOLATED     (1 << 0)    /* Isolated PE      */
0064 #define EEH_PE_RECOVERING   (1 << 1)    /* Recovering PE    */
0065 #define EEH_PE_CFG_BLOCKED  (1 << 2)    /* Block config access  */
0066 #define EEH_PE_RESET        (1 << 3)    /* PE reset in progress */
0067
0068 #define EEH_PE_KEEP     (1 << 8)    /* Keep PE on hotplug   */
0069 #define EEH_PE_CFG_RESTRICTED   (1 << 9)    /* Block config on error */
0070 #define EEH_PE_REMOVED      (1 << 10)   /* Removed permanently  */
0071 #define EEH_PE_PRI_BUS      (1 << 11)   /* Cached primary bus   */
0072
0073 struct eeh_pe {
0074     int type;           /* PE type: PHB/Bus/Device  */
0075     int state;          /* PE EEH dependent mode    */
0076     int addr;           /* PE configuration address */
0077     struct pci_controller *phb; /* Associated PHB       */
0078     struct pci_bus *bus;        /* Top PCI bus for bus PE   */
0079     int check_count;        /* Times of ignored error   */
0080     int freeze_count;       /* Times of froze up        */
0081     time64_t tstamp;        /* Time on first-time freeze    */
0082     int false_positives;        /* Times of reported #ff's  */
0083     atomic_t pass_dev_cnt;      /* Count of passed through devs */
0084     struct eeh_pe *parent;      /* Parent PE            */
0085     void *data;         /* PE auxillary data        */
0086     struct list_head child_list;    /* List of PEs below this PE    */
0087     struct list_head child;     /* Memb. child_list/eeh_phb_pe  */
0088     struct list_head edevs;     /* List of eeh_dev in this PE   */
0089
0090 #ifdef CONFIG_STACKTRACE
0091     /*
0092      * Saved stack trace. When we find a PE freeze in eeh_dev_check_failure
0093      * the stack trace is saved here so we can print it in the recovery
0094      * thread if it turns out to due to a real problem rather than
0095      * a hot-remove.
0096      *
0097      * A max of 64 entries might be overkill, but it also might not be.
0098      */
0099     unsigned long stack_trace[64];
0100     int trace_entries;
0101 #endif /* CONFIG_STACKTRACE */
0102 };
0103
0104 #define eeh_pe_for_each_dev(pe, edev, tmp) \
0105         list_for_each_entry_safe(edev, tmp, &pe->edevs, entry)
0106
0107 #define eeh_for_each_pe(root, pe) \
0108     for (pe = root; pe; pe = eeh_pe_next(pe, root))
0109
0110 static inline bool eeh_pe_passed(struct eeh_pe *pe)
0111 {
0112     return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
0113 }
0114
0115 /*
0116  * The struct is used to trace EEH state for the associated
0117  * PCI device node or PCI device. In future, it might
0118  * represent PE as well so that the EEH device to form
0119  * another tree except the currently existing tree of PCI
0120  * buses and PCI devices
0121  */
0122 #define EEH_DEV_BRIDGE      (1 << 0)    /* PCI bridge       */
0123 #define EEH_DEV_ROOT_PORT   (1 << 1)    /* PCIe root port   */
0124 #define EEH_DEV_DS_PORT     (1 << 2)    /* Downstream port  */
0125 #define EEH_DEV_IRQ_DISABLED    (1 << 3)    /* Interrupt disabled   */
0126 #define EEH_DEV_DISCONNECTED    (1 << 4)    /* Removing from PE */
0127
0128 #define EEH_DEV_NO_HANDLER  (1 << 8)    /* No error handler */
0129 #define EEH_DEV_SYSFS       (1 << 9)    /* Sysfs created    */
0130 #define EEH_DEV_REMOVED     (1 << 10)   /* Removed permanently  */
0131
0132 struct eeh_dev {
0133     int mode;           /* EEH mode         */
0134     int bdfn;           /* bdfn of device (for cfg ops) */
0135     struct pci_controller *controller;
0136     int pe_config_addr;     /* PE config address        */
0137     u32 config_space[16];       /* Saved PCI config space   */
0138     int pcix_cap;           /* Saved PCIx capability    */
0139     int pcie_cap;           /* Saved PCIe capability    */
0140     int aer_cap;            /* Saved AER capability     */
0141     int af_cap;         /* Saved AF capability      */
0142     struct eeh_pe *pe;      /* Associated PE        */
0143     struct list_head entry;     /* Membership in eeh_pe.edevs   */
0144     struct list_head rmv_entry; /* Membership in rmv_list   */
0145     struct pci_dn *pdn;     /* Associated PCI device node   */
0146     struct pci_dev *pdev;       /* Associated PCI device    */
0147     bool in_error;          /* Error flag for edev      */
0148
0149     /* VF specific properties */
0150     struct pci_dev *physfn;     /* Associated SRIOV PF      */
0151     int vf_index;           /* Index of this VF         */
0152 };
0153
0154 /* "fmt" must be a simple literal string */
0155 #define EEH_EDEV_PRINT(level, edev, fmt, ...) \
0156     pr_##level("PCI %04x:%02x:%02x.%x#%04x: EEH: " fmt, \
0157     (edev)->controller->global_number, PCI_BUSNO((edev)->bdfn), \
0158     PCI_SLOT((edev)->bdfn), PCI_FUNC((edev)->bdfn), \
0159     ((edev)->pe ? (edev)->pe_config_addr : 0xffff), ##__VA_ARGS__)
0160 #define eeh_edev_dbg(edev, fmt, ...) EEH_EDEV_PRINT(debug, (edev), fmt, ##__VA_ARGS__)
0161 #define eeh_edev_info(edev, fmt, ...) EEH_EDEV_PRINT(info, (edev), fmt, ##__VA_ARGS__)
0162 #define eeh_edev_warn(edev, fmt, ...) EEH_EDEV_PRINT(warn, (edev), fmt, ##__VA_ARGS__)
0163 #define eeh_edev_err(edev, fmt, ...) EEH_EDEV_PRINT(err, (edev), fmt, ##__VA_ARGS__)
0164
0165 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
0166 {
0167     return edev ? edev->pdn : NULL;
0168 }
0169
0170 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
0171 {
0172     return edev ? edev->pdev : NULL;
0173 }
0174
0175 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
0176 {
0177     return edev ? edev->pe : NULL;
0178 }
0179
0180 /* Return values from eeh_ops::next_error */
0181 enum {
0182     EEH_NEXT_ERR_NONE = 0,
0183     EEH_NEXT_ERR_INF,
0184     EEH_NEXT_ERR_FROZEN_PE,
0185     EEH_NEXT_ERR_FENCED_PHB,
0186     EEH_NEXT_ERR_DEAD_PHB,
0187     EEH_NEXT_ERR_DEAD_IOC
0188 };
0189
0190 /*
0191  * The struct is used to trace the registered EEH operation
0192  * callback functions. Actually, those operation callback
0193  * functions are heavily platform dependent. That means the
0194  * platform should register its own EEH operation callback
0195  * functions before any EEH further operations.
0196  */
0197 #define EEH_OPT_DISABLE     0   /* EEH disable  */
0198 #define EEH_OPT_ENABLE      1   /* EEH enable   */
0199 #define EEH_OPT_THAW_MMIO   2   /* MMIO enable  */
0200 #define EEH_OPT_THAW_DMA    3   /* DMA enable   */
0201 #define EEH_OPT_FREEZE_PE   4   /* Freeze PE    */
0202 #define EEH_STATE_UNAVAILABLE   (1 << 0)    /* State unavailable    */
0203 #define EEH_STATE_NOT_SUPPORT   (1 << 1)    /* EEH not supported    */
0204 #define EEH_STATE_RESET_ACTIVE  (1 << 2)    /* Active reset     */
0205 #define EEH_STATE_MMIO_ACTIVE   (1 << 3)    /* Active MMIO      */
0206 #define EEH_STATE_DMA_ACTIVE    (1 << 4)    /* Active DMA       */
0207 #define EEH_STATE_MMIO_ENABLED  (1 << 5)    /* MMIO enabled     */
0208 #define EEH_STATE_DMA_ENABLED   (1 << 6)    /* DMA enabled      */
0209 #define EEH_RESET_DEACTIVATE    0   /* Deactivate the PE reset  */
0210 #define EEH_RESET_HOT       1   /* Hot reset            */
0211 #define EEH_RESET_FUNDAMENTAL   3   /* Fundamental reset        */
0212 #define EEH_LOG_TEMP        1   /* EEH temporary error log  */
0213 #define EEH_LOG_PERM        2   /* EEH permanent error log  */
0214
0215 struct eeh_ops {
0216     char *name;
0217     struct eeh_dev *(*probe)(struct pci_dev *pdev);
0218     int (*set_option)(struct eeh_pe *pe, int option);
0219     int (*get_state)(struct eeh_pe *pe, int *delay);
0220     int (*reset)(struct eeh_pe *pe, int option);
0221     int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
0222     int (*configure_bridge)(struct eeh_pe *pe);
0223     int (*err_inject)(struct eeh_pe *pe, int type, int func,
0224               unsigned long addr, unsigned long mask);
0225     int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val);
0226     int (*write_config)(struct eeh_dev *edev, int where, int size, u32 val);
0227     int (*next_error)(struct eeh_pe **pe);
0228     int (*restore_config)(struct eeh_dev *edev);
0229     int (*notify_resume)(struct eeh_dev *edev);
0230 };
0231
0232 extern int eeh_subsystem_flags;
0233 extern u32 eeh_max_freezes;
0234 extern bool eeh_debugfs_no_recover;
0235 extern struct eeh_ops *eeh_ops;
0236 extern raw_spinlock_t confirm_error_lock;
0237
0238 static inline void eeh_add_flag(int flag)
0239 {
0240     eeh_subsystem_flags |= flag;
0241 }
0242
0243 static inline void eeh_clear_flag(int flag)
0244 {
0245     eeh_subsystem_flags &= ~flag;
0246 }
0247
0248 static inline bool eeh_has_flag(int flag)
0249 {
0250         return !!(eeh_subsystem_flags & flag);
0251 }
0252
0253 static inline bool eeh_enabled(void)
0254 {
0255     return eeh_has_flag(EEH_ENABLED) && !eeh_has_flag(EEH_FORCE_DISABLED);
0256 }
0257
0258 static inline void eeh_serialize_lock(unsigned long *flags)
0259 {
0260     raw_spin_lock_irqsave(&confirm_error_lock, *flags);
0261 }
0262
0263 static inline void eeh_serialize_unlock(unsigned long flags)
0264 {
0265     raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
0266 }
0267
0268 static inline bool eeh_state_active(int state)
0269 {
0270     return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
0271     == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
0272 }
0273
0274 typedef void (*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
0275 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
0276 void eeh_set_pe_aux_size(int size);
0277 int eeh_phb_pe_create(struct pci_controller *phb);
0278 int eeh_wait_state(struct eeh_pe *pe, int max_wait);
0279 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
0280 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
0281 struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no);
0282 int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent);
0283 int eeh_pe_tree_remove(struct eeh_dev *edev);
0284 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
0285 void *eeh_pe_traverse(struct eeh_pe *root,
0286               eeh_pe_traverse_func fn, void *flag);
0287 void eeh_pe_dev_traverse(struct eeh_pe *root,
0288              eeh_edev_traverse_func fn, void *flag);
0289 void eeh_pe_restore_bars(struct eeh_pe *pe);
0290 const char *eeh_pe_loc_get(struct eeh_pe *pe);
0291 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
0292
0293 void eeh_show_enabled(void);
0294 int __init eeh_init(struct eeh_ops *ops);
0295 int eeh_check_failure(const volatile void __iomem *token);
0296 int eeh_dev_check_failure(struct eeh_dev *edev);
0297 void eeh_addr_cache_init(void);
0298 void eeh_probe_device(struct pci_dev *pdev);
0299 void eeh_remove_device(struct pci_dev *);
0300 int eeh_unfreeze_pe(struct eeh_pe *pe);
0301 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
0302 int eeh_dev_open(struct pci_dev *pdev);
0303 void eeh_dev_release(struct pci_dev *pdev);
0304 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
0305 int eeh_pe_set_option(struct eeh_pe *pe, int option);
0306 int eeh_pe_get_state(struct eeh_pe *pe);
0307 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed);
0308 int eeh_pe_configure(struct eeh_pe *pe);
0309 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
0310               unsigned long addr, unsigned long mask);
0311
0312 /**
0313  * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
0314  *
0315  * If this macro yields TRUE, the caller relays to eeh_check_failure()
0316  * which does further tests out of line.
0317  */
0318 #define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
0319
0320 /*
0321  * Reads from a device which has been isolated by EEH will return
0322  * all 1s.  This macro gives an all-1s value of the given size (in
0323  * bytes: 1, 2, or 4) for comparing with the result of a read.
0324  */
0325 #define EEH_IO_ERROR_VALUE(size)    (~0U >> ((4 - (size)) * 8))
0326
0327 #else /* !CONFIG_EEH */
0328
0329 static inline bool eeh_enabled(void)
0330 {
0331         return false;
0332 }
0333
0334 static inline void eeh_show_enabled(void) { }
0335
0336 static inline int eeh_check_failure(const volatile void __iomem *token)
0337 {
0338     return 0;
0339 }
0340
0341 #define eeh_dev_check_failure(x) (0)
0342
0343 static inline void eeh_addr_cache_init(void) { }
0344
0345 static inline void eeh_probe_device(struct pci_dev *dev) { }
0346
0347 static inline void eeh_remove_device(struct pci_dev *dev) { }
0348
0349 #define EEH_POSSIBLE_ERROR(val, type) (0)
0350 #define EEH_IO_ERROR_VALUE(size) (-1UL)
0351 static inline int eeh_phb_pe_create(struct pci_controller *phb) { return 0; }
0352 #endif /* CONFIG_EEH */
0353
0354 #if defined(CONFIG_PPC_PSERIES) && defined(CONFIG_EEH)
0355 void pseries_eeh_init_edev_recursive(struct pci_dn *pdn);
0356 #endif
0357
0358 #ifdef CONFIG_PPC64
0359 /*
0360  * MMIO read/write operations with EEH support.
0361  */
0362 static inline u8 eeh_readb(const volatile void __iomem *addr)
0363 {
0364     u8 val = in_8(addr);
0365     if (EEH_POSSIBLE_ERROR(val, u8))
0366         eeh_check_failure(addr);
0367     return val;
0368 }
0369
0370 static inline u16 eeh_readw(const volatile void __iomem *addr)
0371 {
0372     u16 val = in_le16(addr);
0373     if (EEH_POSSIBLE_ERROR(val, u16))
0374         eeh_check_failure(addr);
0375     return val;
0376 }
0377
0378 static inline u32 eeh_readl(const volatile void __iomem *addr)
0379 {
0380     u32 val = in_le32(addr);
0381     if (EEH_POSSIBLE_ERROR(val, u32))
0382         eeh_check_failure(addr);
0383     return val;
0384 }
0385
0386 static inline u64 eeh_readq(const volatile void __iomem *addr)
0387 {
0388     u64 val = in_le64(addr);
0389     if (EEH_POSSIBLE_ERROR(val, u64))
0390         eeh_check_failure(addr);
0391     return val;
0392 }
0393
0394 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
0395 {
0396     u16 val = in_be16(addr);
0397     if (EEH_POSSIBLE_ERROR(val, u16))
0398         eeh_check_failure(addr);
0399     return val;
0400 }
0401
0402 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
0403 {
0404     u32 val = in_be32(addr);
0405     if (EEH_POSSIBLE_ERROR(val, u32))
0406         eeh_check_failure(addr);
0407     return val;
0408 }
0409
0410 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
0411 {
0412     u64 val = in_be64(addr);
0413     if (EEH_POSSIBLE_ERROR(val, u64))
0414         eeh_check_failure(addr);
0415     return val;
0416 }
0417
0418 static inline void eeh_memcpy_fromio(void *dest, const
0419                      volatile void __iomem *src,
0420                      unsigned long n)
0421 {
0422     _memcpy_fromio(dest, src, n);
0423
0424     /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
0425      * were copied. Check all four bytes.
0426      */
0427     if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
0428         eeh_check_failure(src);
0429 }
0430
0431 /* in-string eeh macros */
0432 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
0433                   int ns)
0434 {
0435     _insb(addr, buf, ns);
0436     if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
0437         eeh_check_failure(addr);
0438 }
0439
0440 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
0441                   int ns)
0442 {
0443     _insw(addr, buf, ns);
0444     if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
0445         eeh_check_failure(addr);
0446 }
0447
0448 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
0449                   int nl)
0450 {
0451     _insl(addr, buf, nl);
0452     if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
0453         eeh_check_failure(addr);
0454 }
0455
0456
0457 void __init eeh_cache_debugfs_init(void);
0458
0459 #endif /* CONFIG_PPC64 */
0460 #endif /* __KERNEL__ */
0461 #endif /* _POWERPC_EEH_H */