include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_DMA_H
0003 #define _ASM_POWERPC_DMA_H
0004 #ifdef __KERNEL__
0005
0006 /*
0007  * Defines for using and allocating dma channels.
0008  * Written by Hennus Bergman, 1992.
0009  * High DMA channel support & info by Hannu Savolainen
0010  * and John Boyd, Nov. 1992.
0011  * Changes for ppc sound by Christoph Nadig
0012  */
0013
0014 /*
0015  * Note: Adapted for PowerPC by Gary Thomas
0016  * Modified by Cort Dougan <cort@cs.nmt.edu>
0017  *
0018  * None of this really applies for Power Macintoshes.  There is
0019  * basically just enough here to get kernel/dma.c to compile.
0020  */
0021
0022 #include <asm/io.h>
0023 #include <linux/spinlock.h>
0024
0025 #ifndef MAX_DMA_CHANNELS
0026 #define MAX_DMA_CHANNELS    8
0027 #endif
0028
0029 /* The maximum address that we can perform a DMA transfer to on this platform */
0030 /* Doesn't really apply... */
0031 #define MAX_DMA_ADDRESS     (~0UL)
0032
0033 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
0034 #define dma_outb    outb_p
0035 #else
0036 #define dma_outb    outb
0037 #endif
0038
0039 #define dma_inb     inb
0040
0041 /*
0042  * NOTES about DMA transfers:
0043  *
0044  *  controller 1: channels 0-3, byte operations, ports 00-1F
0045  *  controller 2: channels 4-7, word operations, ports C0-DF
0046  *
0047  *  - ALL registers are 8 bits only, regardless of transfer size
0048  *  - channel 4 is not used - cascades 1 into 2.
0049  *  - channels 0-3 are byte - addresses/counts are for physical bytes
0050  *  - channels 5-7 are word - addresses/counts are for physical words
0051  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
0052  *  - transfer count loaded to registers is 1 less than actual count
0053  *  - controller 2 offsets are all even (2x offsets for controller 1)
0054  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
0055  *  - page registers for 0-3 use bit 0, represent 64K pages
0056  *
0057  * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
0058  * Note that addresses loaded into registers must be _physical_ addresses,
0059  * not logical addresses (which may differ if paging is active).
0060  *
0061  *  Address mapping for channels 0-3:
0062  *
0063  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
0064  *    |  ...  |   |  ... |   |  ... |
0065  *    |  ...  |   |  ... |   |  ... |
0066  *    |  ...  |   |  ... |   |  ... |
0067  *   P7  ...  P0  A7 ... A0  A7 ... A0
0068  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
0069  *
0070  *  Address mapping for channels 5-7:
0071  *
0072  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
0073  *    |  ...  |   \   \   ... \  \  \  ... \  \
0074  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
0075  *    |  ...  |     \   \   ... \  \  \  ... \
0076  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
0077  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
0078  *
0079  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
0080  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
0081  * the hardware level, so odd-byte transfers aren't possible).
0082  *
0083  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
0084  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
0085  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
0086  *
0087  */
0088
0089 /* 8237 DMA controllers */
0090 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
0091 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
0092
0093 /* DMA controller registers */
0094 #define DMA1_CMD_REG        0x08    /* command register (w) */
0095 #define DMA1_STAT_REG       0x08    /* status register (r) */
0096 #define DMA1_REQ_REG        0x09    /* request register (w) */
0097 #define DMA1_MASK_REG       0x0A    /* single-channel mask (w) */
0098 #define DMA1_MODE_REG       0x0B    /* mode register (w) */
0099 #define DMA1_CLEAR_FF_REG   0x0C    /* clear pointer flip-flop (w) */
0100 #define DMA1_TEMP_REG       0x0D    /* Temporary Register (r) */
0101 #define DMA1_RESET_REG      0x0D    /* Master Clear (w) */
0102 #define DMA1_CLR_MASK_REG   0x0E    /* Clear Mask */
0103 #define DMA1_MASK_ALL_REG   0x0F    /* all-channels mask (w) */
0104
0105 #define DMA2_CMD_REG        0xD0    /* command register (w) */
0106 #define DMA2_STAT_REG       0xD0    /* status register (r) */
0107 #define DMA2_REQ_REG        0xD2    /* request register (w) */
0108 #define DMA2_MASK_REG       0xD4    /* single-channel mask (w) */
0109 #define DMA2_MODE_REG       0xD6    /* mode register (w) */
0110 #define DMA2_CLEAR_FF_REG   0xD8    /* clear pointer flip-flop (w) */
0111 #define DMA2_TEMP_REG       0xDA    /* Temporary Register (r) */
0112 #define DMA2_RESET_REG      0xDA    /* Master Clear (w) */
0113 #define DMA2_CLR_MASK_REG   0xDC    /* Clear Mask */
0114 #define DMA2_MASK_ALL_REG   0xDE    /* all-channels mask (w) */
0115
0116 #define DMA_ADDR_0      0x00    /* DMA address registers */
0117 #define DMA_ADDR_1      0x02
0118 #define DMA_ADDR_2      0x04
0119 #define DMA_ADDR_3      0x06
0120 #define DMA_ADDR_4      0xC0
0121 #define DMA_ADDR_5      0xC4
0122 #define DMA_ADDR_6      0xC8
0123 #define DMA_ADDR_7      0xCC
0124
0125 #define DMA_CNT_0       0x01    /* DMA count registers */
0126 #define DMA_CNT_1       0x03
0127 #define DMA_CNT_2       0x05
0128 #define DMA_CNT_3       0x07
0129 #define DMA_CNT_4       0xC2
0130 #define DMA_CNT_5       0xC6
0131 #define DMA_CNT_6       0xCA
0132 #define DMA_CNT_7       0xCE
0133
0134 #define DMA_LO_PAGE_0       0x87    /* DMA page registers */
0135 #define DMA_LO_PAGE_1       0x83
0136 #define DMA_LO_PAGE_2       0x81
0137 #define DMA_LO_PAGE_3       0x82
0138 #define DMA_LO_PAGE_5       0x8B
0139 #define DMA_LO_PAGE_6       0x89
0140 #define DMA_LO_PAGE_7       0x8A
0141
0142 #define DMA_HI_PAGE_0       0x487   /* DMA page registers */
0143 #define DMA_HI_PAGE_1       0x483
0144 #define DMA_HI_PAGE_2       0x481
0145 #define DMA_HI_PAGE_3       0x482
0146 #define DMA_HI_PAGE_5       0x48B
0147 #define DMA_HI_PAGE_6       0x489
0148 #define DMA_HI_PAGE_7       0x48A
0149
0150 #define DMA1_EXT_REG        0x40B
0151 #define DMA2_EXT_REG        0x4D6
0152
0153 #ifndef __powerpc64__
0154     /* in arch/powerpc/kernel/setup_32.c -- Cort */
0155     extern unsigned int DMA_MODE_WRITE;
0156     extern unsigned int DMA_MODE_READ;
0157 #else
0158     #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
0159     #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
0160 #endif
0161
0162 #define DMA_MODE_CASCADE    0xC0    /* pass thru DREQ->HRQ, DACK<-HLDA only */
0163
0164 #define DMA_AUTOINIT        0x10
0165
0166 extern spinlock_t dma_spin_lock;
0167
0168 static __inline__ unsigned long claim_dma_lock(void)
0169 {
0170     unsigned long flags;
0171     spin_lock_irqsave(&dma_spin_lock, flags);
0172     return flags;
0173 }
0174
0175 static __inline__ void release_dma_lock(unsigned long flags)
0176 {
0177     spin_unlock_irqrestore(&dma_spin_lock, flags);
0178 }
0179
0180 /* enable/disable a specific DMA channel */
0181 static __inline__ void enable_dma(unsigned int dmanr)
0182 {
0183     unsigned char ucDmaCmd = 0x00;
0184
0185     if (dmanr != 4) {
0186         dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
0187         dma_outb(ucDmaCmd, DMA2_CMD_REG);   /* Enable group */
0188     }
0189     if (dmanr <= 3) {
0190         dma_outb(dmanr, DMA1_MASK_REG);
0191         dma_outb(ucDmaCmd, DMA1_CMD_REG);   /* Enable group */
0192     } else {
0193         dma_outb(dmanr & 3, DMA2_MASK_REG);
0194     }
0195 }
0196
0197 static __inline__ void disable_dma(unsigned int dmanr)
0198 {
0199     if (dmanr <= 3)
0200         dma_outb(dmanr | 4, DMA1_MASK_REG);
0201     else
0202         dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
0203 }
0204
0205 /* Clear the 'DMA Pointer Flip Flop'.
0206  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
0207  * Use this once to initialize the FF to a known state.
0208  * After that, keep track of it. :-)
0209  * --- In order to do that, the DMA routines below should ---
0210  * --- only be used while interrupts are disabled! ---
0211  */
0212 static __inline__ void clear_dma_ff(unsigned int dmanr)
0213 {
0214     if (dmanr <= 3)
0215         dma_outb(0, DMA1_CLEAR_FF_REG);
0216     else
0217         dma_outb(0, DMA2_CLEAR_FF_REG);
0218 }
0219
0220 /* set mode (above) for a specific DMA channel */
0221 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
0222 {
0223     if (dmanr <= 3)
0224         dma_outb(mode | dmanr, DMA1_MODE_REG);
0225     else
0226         dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
0227 }
0228
0229 /* Set only the page register bits of the transfer address.
0230  * This is used for successive transfers when we know the contents of
0231  * the lower 16 bits of the DMA current address register, but a 64k boundary
0232  * may have been crossed.
0233  */
0234 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
0235 {
0236     switch (dmanr) {
0237     case 0:
0238         dma_outb(pagenr, DMA_LO_PAGE_0);
0239         dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
0240         break;
0241     case 1:
0242         dma_outb(pagenr, DMA_LO_PAGE_1);
0243         dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
0244         break;
0245     case 2:
0246         dma_outb(pagenr, DMA_LO_PAGE_2);
0247         dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
0248         break;
0249     case 3:
0250         dma_outb(pagenr, DMA_LO_PAGE_3);
0251         dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
0252         break;
0253     case 5:
0254         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
0255         dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
0256         break;
0257     case 6:
0258         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
0259         dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
0260         break;
0261     case 7:
0262         dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
0263         dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
0264         break;
0265     }
0266 }
0267
0268 /* Set transfer address & page bits for specific DMA channel.
0269  * Assumes dma flipflop is clear.
0270  */
0271 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
0272 {
0273     if (dmanr <= 3) {
0274         dma_outb(phys & 0xff,
0275              ((dmanr & 3) << 1) + IO_DMA1_BASE);
0276         dma_outb((phys >> 8) & 0xff,
0277              ((dmanr & 3) << 1) + IO_DMA1_BASE);
0278     } else {
0279         dma_outb((phys >> 1) & 0xff,
0280              ((dmanr & 3) << 2) + IO_DMA2_BASE);
0281         dma_outb((phys >> 9) & 0xff,
0282              ((dmanr & 3) << 2) + IO_DMA2_BASE);
0283     }
0284     set_dma_page(dmanr, phys >> 16);
0285 }
0286
0287
0288 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
0289  * a specific DMA channel.
0290  * You must ensure the parameters are valid.
0291  * NOTE: from a manual: "the number of transfers is one more
0292  * than the initial word count"! This is taken into account.
0293  * Assumes dma flip-flop is clear.
0294  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
0295  */
0296 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
0297 {
0298     count--;
0299     if (dmanr <= 3) {
0300         dma_outb(count & 0xff,
0301              ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
0302         dma_outb((count >> 8) & 0xff,
0303              ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
0304     } else {
0305         dma_outb((count >> 1) & 0xff,
0306              ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
0307         dma_outb((count >> 9) & 0xff,
0308              ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
0309     }
0310 }
0311
0312
0313 /* Get DMA residue count. After a DMA transfer, this
0314  * should return zero. Reading this while a DMA transfer is
0315  * still in progress will return unpredictable results.
0316  * If called before the channel has been used, it may return 1.
0317  * Otherwise, it returns the number of _bytes_ left to transfer.
0318  *
0319  * Assumes DMA flip-flop is clear.
0320  */
0321 static __inline__ int get_dma_residue(unsigned int dmanr)
0322 {
0323     unsigned int io_port = (dmanr <= 3)
0324         ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
0325         : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
0326
0327     /* using short to get 16-bit wrap around */
0328     unsigned short count;
0329
0330     count = 1 + dma_inb(io_port);
0331     count += dma_inb(io_port) << 8;
0332
0333     return (dmanr <= 3) ? count : (count << 1);
0334 }
0335
0336 /* These are in kernel/dma.c: */
0337
0338 /* reserve a DMA channel */
0339 extern int request_dma(unsigned int dmanr, const char *device_id);
0340 /* release it again */
0341 extern void free_dma(unsigned int dmanr);
0342
0343 #endif /* __KERNEL__ */
0344 #endif  /* _ASM_POWERPC_DMA_H */