include/asm/dbdma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Definitions for using the Apple Descriptor-Based DMA controller
0004  * in Power Macintosh computers.
0005  *
0006  * Copyright (C) 1996 Paul Mackerras.
0007  */
0008
0009 #ifdef __KERNEL__
0010 #ifndef _ASM_DBDMA_H_
0011 #define _ASM_DBDMA_H_
0012 /*
0013  * DBDMA control/status registers.  All little-endian.
0014  */
0015 struct dbdma_regs {
0016     unsigned int control;   /* lets you change bits in status */
0017     unsigned int status;    /* DMA and device status bits (see below) */
0018     unsigned int cmdptr_hi; /* upper 32 bits of command address */
0019     unsigned int cmdptr;    /* (lower 32 bits of) command address (phys) */
0020     unsigned int intr_sel;  /* select interrupt condition bit */
0021     unsigned int br_sel;    /* select branch condition bit */
0022     unsigned int wait_sel;  /* select wait condition bit */
0023     unsigned int xfer_mode;
0024     unsigned int data2ptr_hi;
0025     unsigned int data2ptr;
0026     unsigned int res1;
0027     unsigned int address_hi;
0028     unsigned int br_addr_hi;
0029     unsigned int res2[3];
0030 };
0031
0032 /* Bits in control and status registers */
0033 #define RUN 0x8000
0034 #define PAUSE   0x4000
0035 #define FLUSH   0x2000
0036 #define WAKE    0x1000
0037 #define DEAD    0x0800
0038 #define ACTIVE  0x0400
0039 #define BT  0x0100
0040 #define DEVSTAT 0x00ff
0041
0042 /*
0043  * DBDMA command structure.  These fields are all little-endian!
0044  */
0045 struct dbdma_cmd {
0046     __le16 req_count;   /* requested byte transfer count */
0047     __le16 command;     /* command word (has bit-fields) */
0048     __le32 phy_addr;    /* physical data address */
0049     __le32 cmd_dep;     /* command-dependent field */
0050     __le16 res_count;   /* residual count after completion */
0051     __le16 xfer_status; /* transfer status */
0052 };
0053
0054 /* DBDMA command values in command field */
0055 #define OUTPUT_MORE 0   /* transfer memory data to stream */
0056 #define OUTPUT_LAST 0x1000  /* ditto followed by end marker */
0057 #define INPUT_MORE  0x2000  /* transfer stream data to memory */
0058 #define INPUT_LAST  0x3000  /* ditto, expect end marker */
0059 #define STORE_WORD  0x4000  /* write word (4 bytes) to device reg */
0060 #define LOAD_WORD   0x5000  /* read word (4 bytes) from device reg */
0061 #define DBDMA_NOP   0x6000  /* do nothing */
0062 #define DBDMA_STOP  0x7000  /* suspend processing */
0063
0064 /* Key values in command field */
0065 #define KEY_STREAM0 0   /* usual data stream */
0066 #define KEY_STREAM1 0x100   /* control/status stream */
0067 #define KEY_STREAM2 0x200   /* device-dependent stream */
0068 #define KEY_STREAM3 0x300   /* device-dependent stream */
0069 #define KEY_REGS    0x500   /* device register space */
0070 #define KEY_SYSTEM  0x600   /* system memory-mapped space */
0071 #define KEY_DEVICE  0x700   /* device memory-mapped space */
0072
0073 /* Interrupt control values in command field */
0074 #define INTR_NEVER  0   /* don't interrupt */
0075 #define INTR_IFSET  0x10    /* intr if condition bit is 1 */
0076 #define INTR_IFCLR  0x20    /* intr if condition bit is 0 */
0077 #define INTR_ALWAYS 0x30    /* always interrupt */
0078
0079 /* Branch control values in command field */
0080 #define BR_NEVER    0   /* don't branch */
0081 #define BR_IFSET    0x4 /* branch if condition bit is 1 */
0082 #define BR_IFCLR    0x8 /* branch if condition bit is 0 */
0083 #define BR_ALWAYS   0xc /* always branch */
0084
0085 /* Wait control values in command field */
0086 #define WAIT_NEVER  0   /* don't wait */
0087 #define WAIT_IFSET  1   /* wait if condition bit is 1 */
0088 #define WAIT_IFCLR  2   /* wait if condition bit is 0 */
0089 #define WAIT_ALWAYS 3   /* always wait */
0090
0091 /* Align an address for a DBDMA command structure */
0092 #define DBDMA_ALIGN(x)  (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
0093              & -sizeof(struct dbdma_cmd))
0094
0095 /* Useful macros */
0096 #define DBDMA_DO_STOP(regs) do {                \
0097     out_le32(&((regs)->control), (RUN|FLUSH)<<16);      \
0098     while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH))  \
0099         ; \
0100 } while(0)
0101
0102 #define DBDMA_DO_RESET(regs) do {               \
0103     out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
0104     while(in_le32(&((regs)->status)) & (RUN)) \
0105         ; \
0106 } while(0)
0107
0108 #endif /* _ASM_DBDMA_H_ */
0109 #endif /* __KERNEL__ */