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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_POWERPC_CPUTABLE_H
0003 #define __ASM_POWERPC_CPUTABLE_H
0004 
0005 
0006 #include <linux/types.h>
0007 #include <uapi/asm/cputable.h>
0008 #include <asm/asm-const.h>
0009 
0010 #ifndef __ASSEMBLY__
0011 
0012 /* This structure can grow, it's real size is used by head.S code
0013  * via the mkdefs mechanism.
0014  */
0015 struct cpu_spec;
0016 
0017 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
0018 typedef void (*cpu_restore_t)(void);
0019 
0020 enum powerpc_pmc_type {
0021     PPC_PMC_DEFAULT = 0,
0022     PPC_PMC_IBM = 1,
0023     PPC_PMC_PA6T = 2,
0024     PPC_PMC_G4 = 3,
0025 };
0026 
0027 struct pt_regs;
0028 
0029 extern int machine_check_generic(struct pt_regs *regs);
0030 extern int machine_check_4xx(struct pt_regs *regs);
0031 extern int machine_check_440A(struct pt_regs *regs);
0032 extern int machine_check_e500mc(struct pt_regs *regs);
0033 extern int machine_check_e500(struct pt_regs *regs);
0034 extern int machine_check_47x(struct pt_regs *regs);
0035 int machine_check_8xx(struct pt_regs *regs);
0036 int machine_check_83xx(struct pt_regs *regs);
0037 
0038 extern void cpu_down_flush_e500v2(void);
0039 extern void cpu_down_flush_e500mc(void);
0040 extern void cpu_down_flush_e5500(void);
0041 extern void cpu_down_flush_e6500(void);
0042 
0043 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
0044 struct cpu_spec {
0045     /* CPU is matched via (PVR & pvr_mask) == pvr_value */
0046     unsigned int    pvr_mask;
0047     unsigned int    pvr_value;
0048 
0049     char        *cpu_name;
0050     unsigned long   cpu_features;       /* Kernel features */
0051     unsigned int    cpu_user_features;  /* Userland features */
0052     unsigned int    cpu_user_features2; /* Userland features v2 */
0053     unsigned int    mmu_features;       /* MMU features */
0054 
0055     /* cache line sizes */
0056     unsigned int    icache_bsize;
0057     unsigned int    dcache_bsize;
0058 
0059     /* flush caches inside the current cpu */
0060     void (*cpu_down_flush)(void);
0061 
0062     /* number of performance monitor counters */
0063     unsigned int    num_pmcs;
0064     enum powerpc_pmc_type pmc_type;
0065 
0066     /* this is called to initialize various CPU bits like L1 cache,
0067      * BHT, SPD, etc... from head.S before branching to identify_machine
0068      */
0069     cpu_setup_t cpu_setup;
0070     /* Used to restore cpu setup on secondary processors and at resume */
0071     cpu_restore_t   cpu_restore;
0072 
0073     /* Name of processor class, for the ELF AT_PLATFORM entry */
0074     char        *platform;
0075 
0076     /* Processor specific machine check handling. Return negative
0077      * if the error is fatal, 1 if it was fully recovered and 0 to
0078      * pass up (not CPU originated) */
0079     int     (*machine_check)(struct pt_regs *regs);
0080 
0081     /*
0082      * Processor specific early machine check handler which is
0083      * called in real mode to handle SLB and TLB errors.
0084      */
0085     long        (*machine_check_early)(struct pt_regs *regs);
0086 };
0087 
0088 extern struct cpu_spec      *cur_cpu_spec;
0089 
0090 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
0091 
0092 extern void set_cur_cpu_spec(struct cpu_spec *s);
0093 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0094 extern void identify_cpu_name(unsigned int pvr);
0095 extern void do_feature_fixups(unsigned long value, void *fixup_start,
0096                   void *fixup_end);
0097 
0098 extern const char *powerpc_base_platform;
0099 
0100 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
0101 extern void cpu_feature_keys_init(void);
0102 #else
0103 static inline void cpu_feature_keys_init(void) { }
0104 #endif
0105 
0106 #endif /* __ASSEMBLY__ */
0107 
0108 /* CPU kernel features */
0109 
0110 /* Definitions for features that we have on both 32-bit and 64-bit chips */
0111 #define CPU_FTR_COHERENT_ICACHE     ASM_CONST(0x00000001)
0112 #define CPU_FTR_ALTIVEC         ASM_CONST(0x00000002)
0113 #define CPU_FTR_DBELL           ASM_CONST(0x00000004)
0114 #define CPU_FTR_CAN_NAP         ASM_CONST(0x00000008)
0115 #define CPU_FTR_DEBUG_LVL_EXC       ASM_CONST(0x00000010)
0116 // ASM_CONST(0x00000020) Free
0117 #define CPU_FTR_FPU_UNAVAILABLE     ASM_CONST(0x00000040)
0118 #define CPU_FTR_LWSYNC          ASM_CONST(0x00000080)
0119 #define CPU_FTR_NOEXECUTE       ASM_CONST(0x00000100)
0120 #define CPU_FTR_EMB_HV          ASM_CONST(0x00000200)
0121 
0122 /* Definitions for features that only exist on 32-bit chips */
0123 #ifdef CONFIG_PPC32
0124 #define CPU_FTR_L2CR            ASM_CONST(0x00002000)
0125 #define CPU_FTR_SPEC7450        ASM_CONST(0x00004000)
0126 #define CPU_FTR_TAU         ASM_CONST(0x00008000)
0127 #define CPU_FTR_CAN_DOZE        ASM_CONST(0x00010000)
0128 #define CPU_FTR_L3CR            ASM_CONST(0x00040000)
0129 #define CPU_FTR_L3_DISABLE_NAP      ASM_CONST(0x00080000)
0130 #define CPU_FTR_NAP_DISABLE_L2_PR   ASM_CONST(0x00100000)
0131 #define CPU_FTR_DUAL_PLL_750FX      ASM_CONST(0x00200000)
0132 #define CPU_FTR_NO_DPM          ASM_CONST(0x00400000)
0133 #define CPU_FTR_476_DD2         ASM_CONST(0x00800000)
0134 #define CPU_FTR_NEED_COHERENT       ASM_CONST(0x01000000)
0135 #define CPU_FTR_NO_BTIC         ASM_CONST(0x02000000)
0136 #define CPU_FTR_PPC_LE          ASM_CONST(0x04000000)
0137 #define CPU_FTR_SPE         ASM_CONST(0x10000000)
0138 #define CPU_FTR_NEED_PAIRED_STWCX   ASM_CONST(0x20000000)
0139 #define CPU_FTR_INDEXED_DCR     ASM_CONST(0x40000000)
0140 
0141 #else   /* CONFIG_PPC32 */
0142 /* Define these to 0 for the sake of tests in common code */
0143 #define CPU_FTR_PPC_LE          (0)
0144 #define CPU_FTR_SPE         (0)
0145 #endif
0146 
0147 /*
0148  * Definitions for the 64-bit processor unique features;
0149  * on 32-bit, make the names available but defined to be 0.
0150  */
0151 #ifdef __powerpc64__
0152 #define LONG_ASM_CONST(x)       ASM_CONST(x)
0153 #else
0154 #define LONG_ASM_CONST(x)       0
0155 #endif
0156 
0157 #define CPU_FTR_REAL_LE         LONG_ASM_CONST(0x0000000000001000)
0158 #define CPU_FTR_HVMODE          LONG_ASM_CONST(0x0000000000002000)
0159 #define CPU_FTR_ARCH_206        LONG_ASM_CONST(0x0000000000008000)
0160 #define CPU_FTR_ARCH_207S       LONG_ASM_CONST(0x0000000000010000)
0161 #define CPU_FTR_ARCH_300        LONG_ASM_CONST(0x0000000000020000)
0162 #define CPU_FTR_MMCRA           LONG_ASM_CONST(0x0000000000040000)
0163 #define CPU_FTR_CTRL            LONG_ASM_CONST(0x0000000000080000)
0164 #define CPU_FTR_SMT         LONG_ASM_CONST(0x0000000000100000)
0165 #define CPU_FTR_PAUSE_ZERO      LONG_ASM_CONST(0x0000000000200000)
0166 #define CPU_FTR_PURR            LONG_ASM_CONST(0x0000000000400000)
0167 #define CPU_FTR_CELL_TB_BUG     LONG_ASM_CONST(0x0000000000800000)
0168 #define CPU_FTR_SPURR           LONG_ASM_CONST(0x0000000001000000)
0169 #define CPU_FTR_DSCR            LONG_ASM_CONST(0x0000000002000000)
0170 #define CPU_FTR_VSX         LONG_ASM_CONST(0x0000000004000000)
0171 #define CPU_FTR_SAO         LONG_ASM_CONST(0x0000000008000000)
0172 #define CPU_FTR_CP_USE_DCBTZ        LONG_ASM_CONST(0x0000000010000000)
0173 #define CPU_FTR_UNALIGNED_LD_STD    LONG_ASM_CONST(0x0000000020000000)
0174 #define CPU_FTR_ASYM_SMT        LONG_ASM_CONST(0x0000000040000000)
0175 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
0176 #define CPU_FTR_POPCNTB         LONG_ASM_CONST(0x0000000100000000)
0177 #define CPU_FTR_POPCNTD         LONG_ASM_CONST(0x0000000200000000)
0178 /* LONG_ASM_CONST(0x0000000400000000) Free */
0179 #define CPU_FTR_VMX_COPY        LONG_ASM_CONST(0x0000000800000000)
0180 #define CPU_FTR_TM          LONG_ASM_CONST(0x0000001000000000)
0181 #define CPU_FTR_CFAR            LONG_ASM_CONST(0x0000002000000000)
0182 #define CPU_FTR_HAS_PPR         LONG_ASM_CONST(0x0000004000000000)
0183 #define CPU_FTR_DAWR            LONG_ASM_CONST(0x0000008000000000)
0184 #define CPU_FTR_DABRX           LONG_ASM_CONST(0x0000010000000000)
0185 #define CPU_FTR_PMAO_BUG        LONG_ASM_CONST(0x0000020000000000)
0186 #define CPU_FTR_POWER9_DD2_1        LONG_ASM_CONST(0x0000080000000000)
0187 #define CPU_FTR_P9_TM_HV_ASSIST     LONG_ASM_CONST(0x0000100000000000)
0188 #define CPU_FTR_P9_TM_XER_SO_BUG    LONG_ASM_CONST(0x0000200000000000)
0189 #define CPU_FTR_P9_TLBIE_STQ_BUG    LONG_ASM_CONST(0x0000400000000000)
0190 #define CPU_FTR_P9_TIDR         LONG_ASM_CONST(0x0000800000000000)
0191 #define CPU_FTR_P9_TLBIE_ERAT_BUG   LONG_ASM_CONST(0x0001000000000000)
0192 #define CPU_FTR_P9_RADIX_PREFETCH_BUG   LONG_ASM_CONST(0x0002000000000000)
0193 #define CPU_FTR_ARCH_31         LONG_ASM_CONST(0x0004000000000000)
0194 #define CPU_FTR_DAWR1           LONG_ASM_CONST(0x0008000000000000)
0195 
0196 #ifndef __ASSEMBLY__
0197 
0198 #define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE)
0199 
0200 /* We only set the altivec features if the kernel was compiled with altivec
0201  * support
0202  */
0203 #ifdef CONFIG_ALTIVEC
0204 #define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
0205 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
0206 #else
0207 #define CPU_FTR_ALTIVEC_COMP    0
0208 #define PPC_FEATURE_HAS_ALTIVEC_COMP    0
0209 #endif
0210 
0211 /* We only set the VSX features if the kernel was compiled with VSX
0212  * support
0213  */
0214 #ifdef CONFIG_VSX
0215 #define CPU_FTR_VSX_COMP    CPU_FTR_VSX
0216 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
0217 #else
0218 #define CPU_FTR_VSX_COMP    0
0219 #define PPC_FEATURE_HAS_VSX_COMP    0
0220 #endif
0221 
0222 /* We only set the spe features if the kernel was compiled with spe
0223  * support
0224  */
0225 #ifdef CONFIG_SPE
0226 #define CPU_FTR_SPE_COMP    CPU_FTR_SPE
0227 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
0228 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
0229 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
0230 #else
0231 #define CPU_FTR_SPE_COMP    0
0232 #define PPC_FEATURE_HAS_SPE_COMP    0
0233 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
0234 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
0235 #endif
0236 
0237 /* We only set the TM feature if the kernel was compiled with TM supprt */
0238 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
0239 #define CPU_FTR_TM_COMP         CPU_FTR_TM
0240 #define PPC_FEATURE2_HTM_COMP       PPC_FEATURE2_HTM
0241 #define PPC_FEATURE2_HTM_NOSC_COMP  PPC_FEATURE2_HTM_NOSC
0242 #else
0243 #define CPU_FTR_TM_COMP         0
0244 #define PPC_FEATURE2_HTM_COMP       0
0245 #define PPC_FEATURE2_HTM_NOSC_COMP  0
0246 #endif
0247 
0248 /* We need to mark all pages as being coherent if we're SMP or we have a
0249  * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
0250  * require it for PCI "streaming/prefetch" to work properly.
0251  * This is also required by 52xx family.
0252  */
0253 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
0254     || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
0255     || defined(CONFIG_PPC_MPC52xx)
0256 #define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
0257 #else
0258 #define CPU_FTR_COMMON                  0
0259 #endif
0260 
0261 /* The powersave features NAP & DOZE seems to confuse BDI when
0262    debugging. So if a BDI is used, disable theses
0263  */
0264 #ifndef CONFIG_BDI_SWITCH
0265 #define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
0266 #define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
0267 #else
0268 #define CPU_FTR_MAYBE_CAN_DOZE  0
0269 #define CPU_FTR_MAYBE_CAN_NAP   0
0270 #endif
0271 
0272 #define CPU_FTRS_603    (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
0273         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
0274 #define CPU_FTRS_604    (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
0275 #define CPU_FTRS_740_NOTAU  (CPU_FTR_COMMON | \
0276         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
0277         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
0278 #define CPU_FTRS_740    (CPU_FTR_COMMON | \
0279         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
0280         CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
0281         CPU_FTR_PPC_LE)
0282 #define CPU_FTRS_750    (CPU_FTR_COMMON | \
0283         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
0284         CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
0285         CPU_FTR_PPC_LE)
0286 #define CPU_FTRS_750CL  (CPU_FTRS_750)
0287 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
0288 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
0289 #define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
0290 #define CPU_FTRS_750GX  (CPU_FTRS_750FX)
0291 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
0292         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
0293         CPU_FTR_ALTIVEC_COMP | \
0294         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
0295 #define CPU_FTRS_7400   (CPU_FTR_COMMON | \
0296         CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
0297         CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
0298         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
0299 #define CPU_FTRS_7450_20    (CPU_FTR_COMMON | \
0300         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0301         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
0302         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0303 #define CPU_FTRS_7450_21    (CPU_FTR_COMMON | \
0304         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0305         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
0306         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
0307         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0308 #define CPU_FTRS_7450_23    (CPU_FTR_COMMON | \
0309         CPU_FTR_NEED_PAIRED_STWCX | \
0310         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0311         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
0312         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
0313 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
0314         CPU_FTR_NEED_PAIRED_STWCX | \
0315         CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
0316         CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
0317 #define CPU_FTRS_7455_20    (CPU_FTR_COMMON | \
0318         CPU_FTR_NEED_PAIRED_STWCX | \
0319         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0320         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
0321         CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
0322         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
0323 #define CPU_FTRS_7455   (CPU_FTR_COMMON | \
0324         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0325         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
0326         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0327 #define CPU_FTRS_7447_10    (CPU_FTR_COMMON | \
0328         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0329         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
0330         CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
0331         CPU_FTR_NEED_PAIRED_STWCX)
0332 #define CPU_FTRS_7447   (CPU_FTR_COMMON | \
0333         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0334         CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
0335         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0336 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
0337         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0338         CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
0339         CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0340 #define CPU_FTRS_7448   (CPU_FTR_COMMON | \
0341         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
0342         CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
0343         CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
0344 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
0345 #define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
0346         CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
0347 #define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
0348         CPU_FTR_MAYBE_CAN_NAP | \
0349         CPU_FTR_COMMON  | CPU_FTR_NOEXECUTE)
0350 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
0351         CPU_FTR_MAYBE_CAN_NAP | \
0352         CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE  | CPU_FTR_NOEXECUTE)
0353 #define CPU_FTRS_CLASSIC32  (CPU_FTR_COMMON)
0354 #define CPU_FTRS_8XX    (CPU_FTR_NOEXECUTE)
0355 #define CPU_FTRS_40X    (CPU_FTR_NOEXECUTE)
0356 #define CPU_FTRS_44X    (CPU_FTR_NOEXECUTE)
0357 #define CPU_FTRS_440x6  (CPU_FTR_NOEXECUTE | \
0358         CPU_FTR_INDEXED_DCR)
0359 #define CPU_FTRS_47X    (CPU_FTRS_440x6)
0360 #define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | \
0361         CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
0362         CPU_FTR_NOEXECUTE)
0363 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
0364         CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
0365         CPU_FTR_NOEXECUTE)
0366 #define CPU_FTRS_E500MC ( \
0367         CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
0368         CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
0369 /*
0370  * e5500/e6500 erratum A-006958 is a timebase bug that can use the
0371  * same workaround as CPU_FTR_CELL_TB_BUG.
0372  */
0373 #define CPU_FTRS_E5500  ( \
0374         CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
0375         CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0376         CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
0377 #define CPU_FTRS_E6500  ( \
0378         CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
0379         CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0380         CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
0381         CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
0382 
0383 /* 64-bit CPUs */
0384 #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
0385         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
0386         CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
0387         CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
0388         CPU_FTR_HVMODE | CPU_FTR_DABRX)
0389 #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
0390         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
0391         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0392         CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
0393         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
0394 #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
0395         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
0396         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0397         CPU_FTR_COHERENT_ICACHE | \
0398         CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
0399         CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
0400         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
0401         CPU_FTR_DABRX)
0402 #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
0403         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
0404         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0405         CPU_FTR_COHERENT_ICACHE | \
0406         CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
0407         CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
0408         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0409         CPU_FTR_CFAR | CPU_FTR_HVMODE | \
0410         CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
0411 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
0412         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
0413         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0414         CPU_FTR_COHERENT_ICACHE | \
0415         CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
0416         CPU_FTR_DSCR | CPU_FTR_SAO  | \
0417         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0418         CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
0419         CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
0420         CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
0421 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
0422 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
0423         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
0424         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0425         CPU_FTR_COHERENT_ICACHE | \
0426         CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
0427         CPU_FTR_DSCR | CPU_FTR_SAO  | \
0428         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0429         CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
0430         CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
0431         CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
0432         CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
0433 #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
0434 #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
0435                    CPU_FTR_P9_RADIX_PREFETCH_BUG | \
0436                    CPU_FTR_POWER9_DD2_1)
0437 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
0438                    CPU_FTR_P9_TM_HV_ASSIST | \
0439                    CPU_FTR_P9_TM_XER_SO_BUG)
0440 #define CPU_FTRS_POWER9_DD2_3 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
0441                    CPU_FTR_P9_TM_HV_ASSIST | \
0442                    CPU_FTR_P9_TM_XER_SO_BUG | \
0443                    CPU_FTR_DAWR)
0444 #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
0445         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
0446         CPU_FTR_MMCRA | CPU_FTR_SMT | \
0447         CPU_FTR_COHERENT_ICACHE | \
0448         CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
0449         CPU_FTR_DSCR | CPU_FTR_SAO  | \
0450         CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
0451         CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
0452         CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
0453         CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
0454         CPU_FTR_DAWR | CPU_FTR_DAWR1)
0455 #define CPU_FTRS_CELL   (CPU_FTR_LWSYNC | \
0456         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
0457         CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
0458         CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
0459         CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
0460 #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
0461         CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
0462         CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
0463 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
0464 
0465 #ifdef CONFIG_PPC64
0466 #ifdef CONFIG_PPC_BOOK3E
0467 #define CPU_FTRS_POSSIBLE   (CPU_FTRS_E6500 | CPU_FTRS_E5500)
0468 #else
0469 #ifdef CONFIG_CPU_LITTLE_ENDIAN
0470 #define CPU_FTRS_POSSIBLE   \
0471         (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
0472          CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
0473          CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
0474          CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
0475 #else
0476 #define CPU_FTRS_POSSIBLE   \
0477         (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
0478          CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
0479          CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
0480          CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
0481          CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
0482          CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
0483 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
0484 #endif
0485 #else
0486 enum {
0487     CPU_FTRS_POSSIBLE =
0488 #ifdef CONFIG_PPC_BOOK3S_604
0489         CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
0490         CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
0491         CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
0492         CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
0493         CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
0494         CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
0495         CPU_FTRS_7447 | CPU_FTRS_7447A |
0496         CPU_FTRS_CLASSIC32 |
0497 #endif
0498 #ifdef CONFIG_PPC_BOOK3S_603
0499         CPU_FTRS_603 | CPU_FTRS_82XX |
0500         CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
0501 #endif
0502 #ifdef CONFIG_PPC_8xx
0503         CPU_FTRS_8XX |
0504 #endif
0505 #ifdef CONFIG_40x
0506         CPU_FTRS_40X |
0507 #endif
0508 #ifdef CONFIG_PPC_47x
0509         CPU_FTRS_47X | CPU_FTR_476_DD2 |
0510 #elif defined(CONFIG_44x)
0511         CPU_FTRS_44X | CPU_FTRS_440x6 |
0512 #endif
0513 #ifdef CONFIG_E500
0514         CPU_FTRS_E500 | CPU_FTRS_E500_2 |
0515 #endif
0516 #ifdef CONFIG_PPC_E500MC
0517         CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
0518 #endif
0519         0,
0520 };
0521 #endif /* __powerpc64__ */
0522 
0523 #ifdef CONFIG_PPC64
0524 #ifdef CONFIG_PPC_BOOK3E
0525 #define CPU_FTRS_ALWAYS     (CPU_FTRS_E6500 & CPU_FTRS_E5500)
0526 #else
0527 
0528 #ifdef CONFIG_PPC_DT_CPU_FTRS
0529 #define CPU_FTRS_DT_CPU_BASE            \
0530     (CPU_FTR_LWSYNC |           \
0531      CPU_FTR_FPU_UNAVAILABLE |      \
0532      CPU_FTR_NOEXECUTE |            \
0533      CPU_FTR_COHERENT_ICACHE |      \
0534      CPU_FTR_STCX_CHECKS_ADDRESS |      \
0535      CPU_FTR_POPCNTB | CPU_FTR_POPCNTD |    \
0536      CPU_FTR_DAWR |             \
0537      CPU_FTR_ARCH_206 |         \
0538      CPU_FTR_ARCH_207S)
0539 #else
0540 #define CPU_FTRS_DT_CPU_BASE    (~0ul)
0541 #endif
0542 
0543 #ifdef CONFIG_CPU_LITTLE_ENDIAN
0544 #define CPU_FTRS_ALWAYS \
0545         (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
0546          CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
0547          CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
0548          CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
0549 #else
0550 #define CPU_FTRS_ALWAYS     \
0551         (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
0552          CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
0553          CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
0554          ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
0555          CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
0556          CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
0557 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
0558 #endif
0559 #else
0560 enum {
0561     CPU_FTRS_ALWAYS =
0562 #ifdef CONFIG_PPC_BOOK3S_604
0563         CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
0564         CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
0565         CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
0566         CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
0567         CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
0568         CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
0569         CPU_FTRS_7447 & CPU_FTRS_7447A &
0570         CPU_FTRS_CLASSIC32 &
0571 #endif
0572 #ifdef CONFIG_PPC_BOOK3S_603
0573         CPU_FTRS_603 & CPU_FTRS_82XX &
0574         CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
0575 #endif
0576 #ifdef CONFIG_PPC_8xx
0577         CPU_FTRS_8XX &
0578 #endif
0579 #ifdef CONFIG_40x
0580         CPU_FTRS_40X &
0581 #endif
0582 #ifdef CONFIG_PPC_47x
0583         CPU_FTRS_47X &
0584 #elif defined(CONFIG_44x)
0585         CPU_FTRS_44X & CPU_FTRS_440x6 &
0586 #endif
0587 #ifdef CONFIG_E500
0588         CPU_FTRS_E500 & CPU_FTRS_E500_2 &
0589 #endif
0590 #ifdef CONFIG_PPC_E500MC
0591         CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
0592 #endif
0593         ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
0594         CPU_FTRS_POSSIBLE,
0595 };
0596 #endif /* __powerpc64__ */
0597 
0598 /*
0599  * Maximum number of hw breakpoint supported on powerpc. Number of
0600  * breakpoints supported by actual hw might be less than this, which
0601  * is decided at run time in nr_wp_slots().
0602  */
0603 #define HBP_NUM_MAX 2
0604 
0605 #endif /* !__ASSEMBLY__ */
0606 
0607 #endif /* __ASM_POWERPC_CPUTABLE_H */
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