include/asm/cpuidle.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_CPUIDLE_H
0003 #define _ASM_POWERPC_CPUIDLE_H
0004
0005 #ifdef CONFIG_PPC_POWERNV
0006 /* Thread state used in powernv idle state management */
0007 #define PNV_THREAD_RUNNING              0
0008 #define PNV_THREAD_NAP                  1
0009 #define PNV_THREAD_SLEEP                2
0010 #define PNV_THREAD_WINKLE               3
0011
0012 /*
0013  * Core state used in powernv idle for POWER8.
0014  *
0015  * The lock bit synchronizes updates to the state, as well as parts of the
0016  * sleep/wake code (see kernel/idle_book3s.S).
0017  *
0018  * Bottom 8 bits track the idle state of each thread. Bit is cleared before
0019  * the thread executes an idle instruction (nap/sleep/winkle).
0020  *
0021  * Then there is winkle tracking. A core does not lose complete state
0022  * until every thread is in winkle. So the winkle count field counts the
0023  * number of threads in winkle (small window of false positives is okay
0024  * around the sleep/wake, so long as there are no false negatives).
0025  *
0026  * When the winkle count reaches 8 (the COUNT_ALL_BIT becomes set), then
0027  * the THREAD_WINKLE_BITS are set, which indicate which threads have not
0028  * yet woken from the winkle state.
0029  */
0030 #define NR_PNV_CORE_IDLE_LOCK_BIT       28
0031 #define PNV_CORE_IDLE_LOCK_BIT          (1ULL << NR_PNV_CORE_IDLE_LOCK_BIT)
0032
0033 #define PNV_CORE_IDLE_WINKLE_COUNT_SHIFT    16
0034 #define PNV_CORE_IDLE_WINKLE_COUNT      0x00010000
0035 #define PNV_CORE_IDLE_WINKLE_COUNT_BITS     0x000F0000
0036 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT  8
0037 #define PNV_CORE_IDLE_THREAD_WINKLE_BITS    0x0000FF00
0038
0039 #define PNV_CORE_IDLE_THREAD_BITS           0x000000FF
0040
0041 /*
0042  * ============================ NOTE =================================
0043  * The older firmware populates only the RL field in the psscr_val and
0044  * sets the psscr_mask to 0xf. On such a firmware, the kernel sets the
0045  * remaining PSSCR fields to default values as follows:
0046  *
0047  * - ESL and EC bits are to 1. So wakeup from any stop state will be
0048  *   at vector 0x100.
0049  *
0050  * - MTL and PSLL are set to the maximum allowed value as per the ISA,
0051  *    i.e. 15.
0052  *
0053  * - The Transition Rate, TR is set to the Maximum value 3.
0054  */
0055 #define PSSCR_HV_DEFAULT_VAL    (PSSCR_ESL | PSSCR_EC |         \
0056                 PSSCR_PSLL_MASK | PSSCR_TR_MASK |   \
0057                 PSSCR_MTL_MASK)
0058
0059 #define PSSCR_HV_DEFAULT_MASK   (PSSCR_ESL | PSSCR_EC |         \
0060                 PSSCR_PSLL_MASK | PSSCR_TR_MASK |   \
0061                 PSSCR_MTL_MASK | PSSCR_RL_MASK)
0062 #define PSSCR_EC_SHIFT    20
0063 #define PSSCR_ESL_SHIFT   21
0064 #define GET_PSSCR_EC(x)   (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT)
0065 #define GET_PSSCR_ESL(x)  (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT)
0066 #define GET_PSSCR_RL(x)   ((x) & PSSCR_RL_MASK)
0067
0068 #define ERR_EC_ESL_MISMATCH     -1
0069 #define ERR_DEEP_STATE_ESL_MISMATCH -2
0070
0071 #ifndef __ASSEMBLY__
0072
0073 #define PNV_IDLE_NAME_LEN    16
0074 struct pnv_idle_states_t {
0075     char name[PNV_IDLE_NAME_LEN];
0076     u32 latency_ns;
0077     u32 residency_ns;
0078     u64 psscr_val;
0079     u64 psscr_mask;
0080     u32 flags;
0081     bool valid;
0082 };
0083
0084 extern struct pnv_idle_states_t *pnv_idle_states;
0085 extern int nr_pnv_idle_states;
0086
0087 unsigned long pnv_cpu_offline(unsigned int cpu);
0088 int __init validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);
0089 static inline void report_invalid_psscr_val(u64 psscr_val, int err)
0090 {
0091     switch (err) {
0092     case ERR_EC_ESL_MISMATCH:
0093         pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal",
0094             psscr_val);
0095         break;
0096     case ERR_DEEP_STATE_ESL_MISMATCH:
0097         pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state",
0098             psscr_val);
0099     }
0100 }
0101 #endif
0102
0103 #endif
0104
0105 #endif