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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Communication Processor Module v2.
0004  *
0005  * This file contains structures and information for the communication
0006  * processor channels found in the dual port RAM or parameter RAM.
0007  * All CPM control and status is available through the CPM2 internal
0008  * memory map.  See immap_cpm2.h for details.
0009  */
0010 #ifdef __KERNEL__
0011 #ifndef __CPM2__
0012 #define __CPM2__
0013 
0014 #include <asm/immap_cpm2.h>
0015 #include <asm/cpm.h>
0016 #include <sysdev/fsl_soc.h>
0017 
0018 /* CPM Command register.
0019 */
0020 #define CPM_CR_RST  ((uint)0x80000000)
0021 #define CPM_CR_PAGE ((uint)0x7c000000)
0022 #define CPM_CR_SBLOCK   ((uint)0x03e00000)
0023 #define CPM_CR_FLG  ((uint)0x00010000)
0024 #define CPM_CR_MCN  ((uint)0x00003fc0)
0025 #define CPM_CR_OPCODE   ((uint)0x0000000f)
0026 
0027 /* Device sub-block and page codes.
0028 */
0029 #define CPM_CR_SCC1_SBLOCK  (0x04)
0030 #define CPM_CR_SCC2_SBLOCK  (0x05)
0031 #define CPM_CR_SCC3_SBLOCK  (0x06)
0032 #define CPM_CR_SCC4_SBLOCK  (0x07)
0033 #define CPM_CR_SMC1_SBLOCK  (0x08)
0034 #define CPM_CR_SMC2_SBLOCK  (0x09)
0035 #define CPM_CR_SPI_SBLOCK   (0x0a)
0036 #define CPM_CR_I2C_SBLOCK   (0x0b)
0037 #define CPM_CR_TIMER_SBLOCK (0x0f)
0038 #define CPM_CR_RAND_SBLOCK  (0x0e)
0039 #define CPM_CR_FCC1_SBLOCK  (0x10)
0040 #define CPM_CR_FCC2_SBLOCK  (0x11)
0041 #define CPM_CR_FCC3_SBLOCK  (0x12)
0042 #define CPM_CR_IDMA1_SBLOCK (0x14)
0043 #define CPM_CR_IDMA2_SBLOCK (0x15)
0044 #define CPM_CR_IDMA3_SBLOCK (0x16)
0045 #define CPM_CR_IDMA4_SBLOCK (0x17)
0046 #define CPM_CR_MCC1_SBLOCK  (0x1c)
0047 
0048 #define CPM_CR_FCC_SBLOCK(x)    (x + 0x10)
0049 
0050 #define CPM_CR_SCC1_PAGE    (0x00)
0051 #define CPM_CR_SCC2_PAGE    (0x01)
0052 #define CPM_CR_SCC3_PAGE    (0x02)
0053 #define CPM_CR_SCC4_PAGE    (0x03)
0054 #define CPM_CR_SMC1_PAGE    (0x07)
0055 #define CPM_CR_SMC2_PAGE    (0x08)
0056 #define CPM_CR_SPI_PAGE     (0x09)
0057 #define CPM_CR_I2C_PAGE     (0x0a)
0058 #define CPM_CR_TIMER_PAGE   (0x0a)
0059 #define CPM_CR_RAND_PAGE    (0x0a)
0060 #define CPM_CR_FCC1_PAGE    (0x04)
0061 #define CPM_CR_FCC2_PAGE    (0x05)
0062 #define CPM_CR_FCC3_PAGE    (0x06)
0063 #define CPM_CR_IDMA1_PAGE   (0x07)
0064 #define CPM_CR_IDMA2_PAGE   (0x08)
0065 #define CPM_CR_IDMA3_PAGE   (0x09)
0066 #define CPM_CR_IDMA4_PAGE   (0x0a)
0067 #define CPM_CR_MCC1_PAGE    (0x07)
0068 #define CPM_CR_MCC2_PAGE    (0x08)
0069 
0070 #define CPM_CR_FCC_PAGE(x)  (x + 0x04)
0071 
0072 /* CPM2-specific opcodes (see cpm.h for common opcodes)
0073 */
0074 #define CPM_CR_START_IDMA   ((ushort)0x0009)
0075 
0076 #define mk_cr_cmd(PG, SBC, MCN, OP) \
0077     ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
0078 
0079 /* The number of pages of host memory we allocate for CPM.  This is
0080  * done early in kernel initialization to get physically contiguous
0081  * pages.
0082  */
0083 #define NUM_CPM_HOST_PAGES  2
0084 
0085 /* Export the base address of the communication processor registers
0086  * and dual port ram.
0087  */
0088 extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
0089 
0090 #define cpm_dpalloc cpm_muram_alloc
0091 #define cpm_dpfree cpm_muram_free
0092 #define cpm_dpram_addr cpm_muram_addr
0093 
0094 extern void cpm2_reset(void);
0095 
0096 /* Baud rate generators.
0097 */
0098 #define CPM_BRG_RST     ((uint)0x00020000)
0099 #define CPM_BRG_EN      ((uint)0x00010000)
0100 #define CPM_BRG_EXTC_INT    ((uint)0x00000000)
0101 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
0102 #define CPM_BRG_EXTC_CLK5_15    ((uint)0x00008000)
0103 #define CPM_BRG_ATB     ((uint)0x00002000)
0104 #define CPM_BRG_CD_MASK     ((uint)0x00001ffe)
0105 #define CPM_BRG_DIV16       ((uint)0x00000001)
0106 
0107 #define CPM2_BRG_INT_CLK    (get_brgfreq())
0108 #define CPM2_BRG_UART_CLK   (CPM2_BRG_INT_CLK/16)
0109 
0110 extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
0111 
0112 /* This function is used by UARTS, or anything else that uses a 16x
0113  * oversampled clock.
0114  */
0115 static inline void cpm_setbrg(uint brg, uint rate)
0116 {
0117     __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
0118 }
0119 
0120 /* This function is used to set high speed synchronous baud rate
0121  * clocks.
0122  */
0123 static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
0124 {
0125     __cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
0126 }
0127 
0128 /* Parameter RAM offsets from the base.
0129 */
0130 #define PROFF_SCC1      ((uint)0x8000)
0131 #define PROFF_SCC2      ((uint)0x8100)
0132 #define PROFF_SCC3      ((uint)0x8200)
0133 #define PROFF_SCC4      ((uint)0x8300)
0134 #define PROFF_FCC1      ((uint)0x8400)
0135 #define PROFF_FCC2      ((uint)0x8500)
0136 #define PROFF_FCC3      ((uint)0x8600)
0137 #define PROFF_MCC1      ((uint)0x8700)
0138 #define PROFF_SMC1_BASE     ((uint)0x87fc)
0139 #define PROFF_IDMA1_BASE    ((uint)0x87fe)
0140 #define PROFF_MCC2      ((uint)0x8800)
0141 #define PROFF_SMC2_BASE     ((uint)0x88fc)
0142 #define PROFF_IDMA2_BASE    ((uint)0x88fe)
0143 #define PROFF_SPI_BASE      ((uint)0x89fc)
0144 #define PROFF_IDMA3_BASE    ((uint)0x89fe)
0145 #define PROFF_TIMERS        ((uint)0x8ae0)
0146 #define PROFF_REVNUM        ((uint)0x8af0)
0147 #define PROFF_RAND      ((uint)0x8af8)
0148 #define PROFF_I2C_BASE      ((uint)0x8afc)
0149 #define PROFF_IDMA4_BASE    ((uint)0x8afe)
0150 
0151 #define PROFF_SCC_SIZE      ((uint)0x100)
0152 #define PROFF_FCC_SIZE      ((uint)0x100)
0153 #define PROFF_SMC_SIZE      ((uint)64)
0154 
0155 /* The SMCs are relocated to any of the first eight DPRAM pages.
0156  * We will fix these at the first locations of DPRAM, until we
0157  * get some microcode patches :-).
0158  * The parameter ram space for the SMCs is fifty-some bytes, and
0159  * they are required to start on a 64 byte boundary.
0160  */
0161 #define PROFF_SMC1  (0)
0162 #define PROFF_SMC2  (64)
0163 
0164 
0165 /* Define enough so I can at least use the serial port as a UART.
0166  */
0167 typedef struct smc_uart {
0168     ushort  smc_rbase;  /* Rx Buffer descriptor base address */
0169     ushort  smc_tbase;  /* Tx Buffer descriptor base address */
0170     u_char  smc_rfcr;   /* Rx function code */
0171     u_char  smc_tfcr;   /* Tx function code */
0172     ushort  smc_mrblr;  /* Max receive buffer length */
0173     uint    smc_rstate; /* Internal */
0174     uint    smc_idp;    /* Internal */
0175     ushort  smc_rbptr;  /* Internal */
0176     ushort  smc_ibc;    /* Internal */
0177     uint    smc_rxtmp;  /* Internal */
0178     uint    smc_tstate; /* Internal */
0179     uint    smc_tdp;    /* Internal */
0180     ushort  smc_tbptr;  /* Internal */
0181     ushort  smc_tbc;    /* Internal */
0182     uint    smc_txtmp;  /* Internal */
0183     ushort  smc_maxidl; /* Maximum idle characters */
0184     ushort  smc_tmpidl; /* Temporary idle counter */
0185     ushort  smc_brklen; /* Last received break length */
0186     ushort  smc_brkec;  /* rcv'd break condition counter */
0187     ushort  smc_brkcr;  /* xmt break count register */
0188     ushort  smc_rmask;  /* Temporary bit mask */
0189     uint    smc_stmp;   /* SDMA Temp */
0190 } smc_uart_t;
0191 
0192 /* SMC uart mode register (Internal memory map).
0193 */
0194 #define SMCMR_REN   ((ushort)0x0001)
0195 #define SMCMR_TEN   ((ushort)0x0002)
0196 #define SMCMR_DM    ((ushort)0x000c)
0197 #define SMCMR_SM_GCI    ((ushort)0x0000)
0198 #define SMCMR_SM_UART   ((ushort)0x0020)
0199 #define SMCMR_SM_TRANS  ((ushort)0x0030)
0200 #define SMCMR_SM_MASK   ((ushort)0x0030)
0201 #define SMCMR_PM_EVEN   ((ushort)0x0100)    /* Even parity, else odd */
0202 #define SMCMR_REVD  SMCMR_PM_EVEN
0203 #define SMCMR_PEN   ((ushort)0x0200)    /* Parity enable */
0204 #define SMCMR_BS    SMCMR_PEN
0205 #define SMCMR_SL    ((ushort)0x0400)    /* Two stops, else one */
0206 #define SMCR_CLEN_MASK  ((ushort)0x7800)    /* Character length */
0207 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
0208 
0209 /* SMC Event and Mask register.
0210 */
0211 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
0212 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
0213 #define SMCM_TXE    ((unsigned char)0x10)
0214 #define SMCM_BSY    ((unsigned char)0x04)
0215 #define SMCM_TX     ((unsigned char)0x02)
0216 #define SMCM_RX     ((unsigned char)0x01)
0217 
0218 /* SCCs.
0219 */
0220 #define SCC_GSMRH_IRP       ((uint)0x00040000)
0221 #define SCC_GSMRH_GDE       ((uint)0x00010000)
0222 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
0223 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
0224 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
0225 #define SCC_GSMRH_REVD      ((uint)0x00002000)
0226 #define SCC_GSMRH_TRX       ((uint)0x00001000)
0227 #define SCC_GSMRH_TTX       ((uint)0x00000800)
0228 #define SCC_GSMRH_CDP       ((uint)0x00000400)
0229 #define SCC_GSMRH_CTSP      ((uint)0x00000200)
0230 #define SCC_GSMRH_CDS       ((uint)0x00000100)
0231 #define SCC_GSMRH_CTSS      ((uint)0x00000080)
0232 #define SCC_GSMRH_TFL       ((uint)0x00000040)
0233 #define SCC_GSMRH_RFW       ((uint)0x00000020)
0234 #define SCC_GSMRH_TXSY      ((uint)0x00000010)
0235 #define SCC_GSMRH_SYNL16    ((uint)0x0000000c)
0236 #define SCC_GSMRH_SYNL8     ((uint)0x00000008)
0237 #define SCC_GSMRH_SYNL4     ((uint)0x00000004)
0238 #define SCC_GSMRH_RTSM      ((uint)0x00000002)
0239 #define SCC_GSMRH_RSYN      ((uint)0x00000001)
0240 
0241 #define SCC_GSMRL_SIR       ((uint)0x80000000)  /* SCC2 only */
0242 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
0243 #define SCC_GSMRL_EDGE_NEG  ((uint)0x40000000)
0244 #define SCC_GSMRL_EDGE_POS  ((uint)0x20000000)
0245 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
0246 #define SCC_GSMRL_TCI       ((uint)0x10000000)
0247 #define SCC_GSMRL_TSNC_3    ((uint)0x0c000000)
0248 #define SCC_GSMRL_TSNC_4    ((uint)0x08000000)
0249 #define SCC_GSMRL_TSNC_14   ((uint)0x04000000)
0250 #define SCC_GSMRL_TSNC_INF  ((uint)0x00000000)
0251 #define SCC_GSMRL_RINV      ((uint)0x02000000)
0252 #define SCC_GSMRL_TINV      ((uint)0x01000000)
0253 #define SCC_GSMRL_TPL_128   ((uint)0x00c00000)
0254 #define SCC_GSMRL_TPL_64    ((uint)0x00a00000)
0255 #define SCC_GSMRL_TPL_48    ((uint)0x00800000)
0256 #define SCC_GSMRL_TPL_32    ((uint)0x00600000)
0257 #define SCC_GSMRL_TPL_16    ((uint)0x00400000)
0258 #define SCC_GSMRL_TPL_8     ((uint)0x00200000)
0259 #define SCC_GSMRL_TPL_NONE  ((uint)0x00000000)
0260 #define SCC_GSMRL_TPP_ALL1  ((uint)0x00180000)
0261 #define SCC_GSMRL_TPP_01    ((uint)0x00100000)
0262 #define SCC_GSMRL_TPP_10    ((uint)0x00080000)
0263 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
0264 #define SCC_GSMRL_TEND      ((uint)0x00040000)
0265 #define SCC_GSMRL_TDCR_32   ((uint)0x00030000)
0266 #define SCC_GSMRL_TDCR_16   ((uint)0x00020000)
0267 #define SCC_GSMRL_TDCR_8    ((uint)0x00010000)
0268 #define SCC_GSMRL_TDCR_1    ((uint)0x00000000)
0269 #define SCC_GSMRL_RDCR_32   ((uint)0x0000c000)
0270 #define SCC_GSMRL_RDCR_16   ((uint)0x00008000)
0271 #define SCC_GSMRL_RDCR_8    ((uint)0x00004000)
0272 #define SCC_GSMRL_RDCR_1    ((uint)0x00000000)
0273 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
0274 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
0275 #define SCC_GSMRL_RENC_FM0  ((uint)0x00001000)
0276 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
0277 #define SCC_GSMRL_RENC_NRZ  ((uint)0x00000000)
0278 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
0279 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
0280 #define SCC_GSMRL_TENC_FM0  ((uint)0x00000200)
0281 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
0282 #define SCC_GSMRL_TENC_NRZ  ((uint)0x00000000)
0283 #define SCC_GSMRL_DIAG_LE   ((uint)0x000000c0)  /* Loop and echo */
0284 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
0285 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
0286 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
0287 #define SCC_GSMRL_ENR       ((uint)0x00000020)
0288 #define SCC_GSMRL_ENT       ((uint)0x00000010)
0289 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
0290 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
0291 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
0292 #define SCC_GSMRL_MODE_V14  ((uint)0x00000007)
0293 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
0294 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
0295 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
0296 #define SCC_GSMRL_MODE_SS7  ((uint)0x00000003)
0297 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
0298 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
0299 
0300 #define SCC_TODR_TOD        ((ushort)0x8000)
0301 
0302 /* SCC Event and Mask register.
0303 */
0304 #define SCCM_TXE    ((unsigned char)0x10)
0305 #define SCCM_BSY    ((unsigned char)0x04)
0306 #define SCCM_TX     ((unsigned char)0x02)
0307 #define SCCM_RX     ((unsigned char)0x01)
0308 
0309 typedef struct scc_param {
0310     ushort  scc_rbase;  /* Rx Buffer descriptor base address */
0311     ushort  scc_tbase;  /* Tx Buffer descriptor base address */
0312     u_char  scc_rfcr;   /* Rx function code */
0313     u_char  scc_tfcr;   /* Tx function code */
0314     ushort  scc_mrblr;  /* Max receive buffer length */
0315     uint    scc_rstate; /* Internal */
0316     uint    scc_idp;    /* Internal */
0317     ushort  scc_rbptr;  /* Internal */
0318     ushort  scc_ibc;    /* Internal */
0319     uint    scc_rxtmp;  /* Internal */
0320     uint    scc_tstate; /* Internal */
0321     uint    scc_tdp;    /* Internal */
0322     ushort  scc_tbptr;  /* Internal */
0323     ushort  scc_tbc;    /* Internal */
0324     uint    scc_txtmp;  /* Internal */
0325     uint    scc_rcrc;   /* Internal */
0326     uint    scc_tcrc;   /* Internal */
0327 } sccp_t;
0328 
0329 /* Function code bits.
0330 */
0331 #define SCC_EB  ((u_char) 0x10) /* Set big endian byte order */
0332 #define SCC_GBL ((u_char) 0x20) /* Snooping enabled */
0333 
0334 /* CPM Ethernet through SCC1.
0335  */
0336 typedef struct scc_enet {
0337     sccp_t  sen_genscc;
0338     uint    sen_cpres;  /* Preset CRC */
0339     uint    sen_cmask;  /* Constant mask for CRC */
0340     uint    sen_crcec;  /* CRC Error counter */
0341     uint    sen_alec;   /* alignment error counter */
0342     uint    sen_disfc;  /* discard frame counter */
0343     ushort  sen_pads;   /* Tx short frame pad character */
0344     ushort  sen_retlim; /* Retry limit threshold */
0345     ushort  sen_retcnt; /* Retry limit counter */
0346     ushort  sen_maxflr; /* maximum frame length register */
0347     ushort  sen_minflr; /* minimum frame length register */
0348     ushort  sen_maxd1;  /* maximum DMA1 length */
0349     ushort  sen_maxd2;  /* maximum DMA2 length */
0350     ushort  sen_maxd;   /* Rx max DMA */
0351     ushort  sen_dmacnt; /* Rx DMA counter */
0352     ushort  sen_maxb;   /* Max BD byte count */
0353     ushort  sen_gaddr1; /* Group address filter */
0354     ushort  sen_gaddr2;
0355     ushort  sen_gaddr3;
0356     ushort  sen_gaddr4;
0357     uint    sen_tbuf0data0; /* Save area 0 - current frame */
0358     uint    sen_tbuf0data1; /* Save area 1 - current frame */
0359     uint    sen_tbuf0rba;   /* Internal */
0360     uint    sen_tbuf0crc;   /* Internal */
0361     ushort  sen_tbuf0bcnt;  /* Internal */
0362     ushort  sen_paddrh; /* physical address (MSB) */
0363     ushort  sen_paddrm;
0364     ushort  sen_paddrl; /* physical address (LSB) */
0365     ushort  sen_pper;   /* persistence */
0366     ushort  sen_rfbdptr;    /* Rx first BD pointer */
0367     ushort  sen_tfbdptr;    /* Tx first BD pointer */
0368     ushort  sen_tlbdptr;    /* Tx last BD pointer */
0369     uint    sen_tbuf1data0; /* Save area 0 - current frame */
0370     uint    sen_tbuf1data1; /* Save area 1 - current frame */
0371     uint    sen_tbuf1rba;   /* Internal */
0372     uint    sen_tbuf1crc;   /* Internal */
0373     ushort  sen_tbuf1bcnt;  /* Internal */
0374     ushort  sen_txlen;  /* Tx Frame length counter */
0375     ushort  sen_iaddr1; /* Individual address filter */
0376     ushort  sen_iaddr2;
0377     ushort  sen_iaddr3;
0378     ushort  sen_iaddr4;
0379     ushort  sen_boffcnt;    /* Backoff counter */
0380 
0381     /* NOTE: Some versions of the manual have the following items
0382      * incorrectly documented.  Below is the proper order.
0383      */
0384     ushort  sen_taddrh; /* temp address (MSB) */
0385     ushort  sen_taddrm;
0386     ushort  sen_taddrl; /* temp address (LSB) */
0387 } scc_enet_t;
0388 
0389 
0390 /* SCC Event register as used by Ethernet.
0391 */
0392 #define SCCE_ENET_GRA   ((ushort)0x0080)    /* Graceful stop complete */
0393 #define SCCE_ENET_TXE   ((ushort)0x0010)    /* Transmit Error */
0394 #define SCCE_ENET_RXF   ((ushort)0x0008)    /* Full frame received */
0395 #define SCCE_ENET_BSY   ((ushort)0x0004)    /* All incoming buffers full */
0396 #define SCCE_ENET_TXB   ((ushort)0x0002)    /* A buffer was transmitted */
0397 #define SCCE_ENET_RXB   ((ushort)0x0001)    /* A buffer was received */
0398 
0399 /* SCC Mode Register (PSMR) as used by Ethernet.
0400 */
0401 #define SCC_PSMR_HBC    ((ushort)0x8000)    /* Enable heartbeat */
0402 #define SCC_PSMR_FC ((ushort)0x4000)    /* Force collision */
0403 #define SCC_PSMR_RSH    ((ushort)0x2000)    /* Receive short frames */
0404 #define SCC_PSMR_IAM    ((ushort)0x1000)    /* Check individual hash */
0405 #define SCC_PSMR_ENCRC  ((ushort)0x0800)    /* Ethernet CRC mode */
0406 #define SCC_PSMR_PRO    ((ushort)0x0200)    /* Promiscuous mode */
0407 #define SCC_PSMR_BRO    ((ushort)0x0100)    /* Catch broadcast pkts */
0408 #define SCC_PSMR_SBT    ((ushort)0x0080)    /* Special backoff timer */
0409 #define SCC_PSMR_LPB    ((ushort)0x0040)    /* Set Loopback mode */
0410 #define SCC_PSMR_SIP    ((ushort)0x0020)    /* Sample Input Pins */
0411 #define SCC_PSMR_LCW    ((ushort)0x0010)    /* Late collision window */
0412 #define SCC_PSMR_NIB22  ((ushort)0x000a)    /* Start frame search */
0413 #define SCC_PSMR_FDE    ((ushort)0x0001)    /* Full duplex enable */
0414 
0415 /* SCC as UART
0416 */
0417 typedef struct scc_uart {
0418     sccp_t  scc_genscc;
0419     uint    scc_res1;   /* Reserved */
0420     uint    scc_res2;   /* Reserved */
0421     ushort  scc_maxidl; /* Maximum idle chars */
0422     ushort  scc_idlc;   /* temp idle counter */
0423     ushort  scc_brkcr;  /* Break count register */
0424     ushort  scc_parec;  /* receive parity error counter */
0425     ushort  scc_frmec;  /* receive framing error counter */
0426     ushort  scc_nosec;  /* receive noise counter */
0427     ushort  scc_brkec;  /* receive break condition counter */
0428     ushort  scc_brkln;  /* last received break length */
0429     ushort  scc_uaddr1; /* UART address character 1 */
0430     ushort  scc_uaddr2; /* UART address character 2 */
0431     ushort  scc_rtemp;  /* Temp storage */
0432     ushort  scc_toseq;  /* Transmit out of sequence char */
0433     ushort  scc_char1;  /* control character 1 */
0434     ushort  scc_char2;  /* control character 2 */
0435     ushort  scc_char3;  /* control character 3 */
0436     ushort  scc_char4;  /* control character 4 */
0437     ushort  scc_char5;  /* control character 5 */
0438     ushort  scc_char6;  /* control character 6 */
0439     ushort  scc_char7;  /* control character 7 */
0440     ushort  scc_char8;  /* control character 8 */
0441     ushort  scc_rccm;   /* receive control character mask */
0442     ushort  scc_rccr;   /* receive control character register */
0443     ushort  scc_rlbc;   /* receive last break character */
0444 } scc_uart_t;
0445 
0446 /* SCC Event and Mask registers when it is used as a UART.
0447 */
0448 #define UART_SCCM_GLR       ((ushort)0x1000)
0449 #define UART_SCCM_GLT       ((ushort)0x0800)
0450 #define UART_SCCM_AB        ((ushort)0x0200)
0451 #define UART_SCCM_IDL       ((ushort)0x0100)
0452 #define UART_SCCM_GRA       ((ushort)0x0080)
0453 #define UART_SCCM_BRKE      ((ushort)0x0040)
0454 #define UART_SCCM_BRKS      ((ushort)0x0020)
0455 #define UART_SCCM_CCR       ((ushort)0x0008)
0456 #define UART_SCCM_BSY       ((ushort)0x0004)
0457 #define UART_SCCM_TX        ((ushort)0x0002)
0458 #define UART_SCCM_RX        ((ushort)0x0001)
0459 
0460 /* The SCC PSMR when used as a UART.
0461 */
0462 #define SCU_PSMR_FLC        ((ushort)0x8000)
0463 #define SCU_PSMR_SL     ((ushort)0x4000)
0464 #define SCU_PSMR_CL     ((ushort)0x3000)
0465 #define SCU_PSMR_UM     ((ushort)0x0c00)
0466 #define SCU_PSMR_FRZ        ((ushort)0x0200)
0467 #define SCU_PSMR_RZS        ((ushort)0x0100)
0468 #define SCU_PSMR_SYN        ((ushort)0x0080)
0469 #define SCU_PSMR_DRT        ((ushort)0x0040)
0470 #define SCU_PSMR_PEN        ((ushort)0x0010)
0471 #define SCU_PSMR_RPM        ((ushort)0x000c)
0472 #define SCU_PSMR_REVP       ((ushort)0x0008)
0473 #define SCU_PSMR_TPM        ((ushort)0x0003)
0474 #define SCU_PSMR_TEVP       ((ushort)0x0002)
0475 
0476 /* CPM Transparent mode SCC.
0477  */
0478 typedef struct scc_trans {
0479     sccp_t  st_genscc;
0480     uint    st_cpres;   /* Preset CRC */
0481     uint    st_cmask;   /* Constant mask for CRC */
0482 } scc_trans_t;
0483 
0484 /* How about some FCCs.....
0485 */
0486 #define FCC_GFMR_DIAG_NORM  ((uint)0x00000000)
0487 #define FCC_GFMR_DIAG_LE    ((uint)0x40000000)
0488 #define FCC_GFMR_DIAG_AE    ((uint)0x80000000)
0489 #define FCC_GFMR_DIAG_ALE   ((uint)0xc0000000)
0490 #define FCC_GFMR_TCI        ((uint)0x20000000)
0491 #define FCC_GFMR_TRX        ((uint)0x10000000)
0492 #define FCC_GFMR_TTX        ((uint)0x08000000)
0493 #define FCC_GFMR_CDP        ((uint)0x04000000)
0494 #define FCC_GFMR_CTSP       ((uint)0x02000000)
0495 #define FCC_GFMR_CDS        ((uint)0x01000000)
0496 #define FCC_GFMR_CTSS       ((uint)0x00800000)
0497 #define FCC_GFMR_SYNL_NONE  ((uint)0x00000000)
0498 #define FCC_GFMR_SYNL_AUTO  ((uint)0x00004000)
0499 #define FCC_GFMR_SYNL_8     ((uint)0x00008000)
0500 #define FCC_GFMR_SYNL_16    ((uint)0x0000c000)
0501 #define FCC_GFMR_RTSM       ((uint)0x00002000)
0502 #define FCC_GFMR_RENC_NRZ   ((uint)0x00000000)
0503 #define FCC_GFMR_RENC_NRZI  ((uint)0x00000800)
0504 #define FCC_GFMR_REVD       ((uint)0x00000400)
0505 #define FCC_GFMR_TENC_NRZ   ((uint)0x00000000)
0506 #define FCC_GFMR_TENC_NRZI  ((uint)0x00000100)
0507 #define FCC_GFMR_TCRC_16    ((uint)0x00000000)
0508 #define FCC_GFMR_TCRC_32    ((uint)0x00000080)
0509 #define FCC_GFMR_ENR        ((uint)0x00000020)
0510 #define FCC_GFMR_ENT        ((uint)0x00000010)
0511 #define FCC_GFMR_MODE_ENET  ((uint)0x0000000c)
0512 #define FCC_GFMR_MODE_ATM   ((uint)0x0000000a)
0513 #define FCC_GFMR_MODE_HDLC  ((uint)0x00000000)
0514 
0515 /* Generic FCC parameter ram.
0516 */
0517 typedef struct fcc_param {
0518     ushort  fcc_riptr;  /* Rx Internal temp pointer */
0519     ushort  fcc_tiptr;  /* Tx Internal temp pointer */
0520     ushort  fcc_res1;
0521     ushort  fcc_mrblr;  /* Max receive buffer length, mod 32 bytes */
0522     uint    fcc_rstate; /* Upper byte is Func code, must be set */
0523     uint    fcc_rbase;  /* Receive BD base */
0524     ushort  fcc_rbdstat;    /* RxBD status */
0525     ushort  fcc_rbdlen; /* RxBD down counter */
0526     uint    fcc_rdptr;  /* RxBD internal data pointer */
0527     uint    fcc_tstate; /* Upper byte is Func code, must be set */
0528     uint    fcc_tbase;  /* Transmit BD base */
0529     ushort  fcc_tbdstat;    /* TxBD status */
0530     ushort  fcc_tbdlen; /* TxBD down counter */
0531     uint    fcc_tdptr;  /* TxBD internal data pointer */
0532     uint    fcc_rbptr;  /* Rx BD Internal buf pointer */
0533     uint    fcc_tbptr;  /* Tx BD Internal buf pointer */
0534     uint    fcc_rcrc;   /* Rx temp CRC */
0535     uint    fcc_res2;
0536     uint    fcc_tcrc;   /* Tx temp CRC */
0537 } fccp_t;
0538 
0539 
0540 /* Ethernet controller through FCC.
0541 */
0542 typedef struct fcc_enet {
0543     fccp_t  fen_genfcc;
0544     uint    fen_statbuf;    /* Internal status buffer */
0545     uint    fen_camptr; /* CAM address */
0546     uint    fen_cmask;  /* Constant mask for CRC */
0547     uint    fen_cpres;  /* Preset CRC */
0548     uint    fen_crcec;  /* CRC Error counter */
0549     uint    fen_alec;   /* alignment error counter */
0550     uint    fen_disfc;  /* discard frame counter */
0551     ushort  fen_retlim; /* Retry limit */
0552     ushort  fen_retcnt; /* Retry counter */
0553     ushort  fen_pper;   /* Persistence */
0554     ushort  fen_boffcnt;    /* backoff counter */
0555     uint    fen_gaddrh; /* Group address filter, high 32-bits */
0556     uint    fen_gaddrl; /* Group address filter, low 32-bits */
0557     ushort  fen_tfcstat;    /* out of sequence TxBD */
0558     ushort  fen_tfclen;
0559     uint    fen_tfcptr;
0560     ushort  fen_mflr;   /* Maximum frame length (1518) */
0561     ushort  fen_paddrh; /* MAC address */
0562     ushort  fen_paddrm;
0563     ushort  fen_paddrl;
0564     ushort  fen_ibdcount;   /* Internal BD counter */
0565     ushort  fen_ibdstart;   /* Internal BD start pointer */
0566     ushort  fen_ibdend; /* Internal BD end pointer */
0567     ushort  fen_txlen;  /* Internal Tx frame length counter */
0568     uint    fen_ibdbase[8]; /* Internal use */
0569     uint    fen_iaddrh; /* Individual address filter */
0570     uint    fen_iaddrl;
0571     ushort  fen_minflr; /* Minimum frame length (64) */
0572     ushort  fen_taddrh; /* Filter transfer MAC address */
0573     ushort  fen_taddrm;
0574     ushort  fen_taddrl;
0575     ushort  fen_padptr; /* Pointer to pad byte buffer */
0576     ushort  fen_cftype; /* control frame type */
0577     ushort  fen_cfrange;    /* control frame range */
0578     ushort  fen_maxb;   /* maximum BD count */
0579     ushort  fen_maxd1;  /* Max DMA1 length (1520) */
0580     ushort  fen_maxd2;  /* Max DMA2 length (1520) */
0581     ushort  fen_maxd;   /* internal max DMA count */
0582     ushort  fen_dmacnt; /* internal DMA counter */
0583     uint    fen_octc;   /* Total octect counter */
0584     uint    fen_colc;   /* Total collision counter */
0585     uint    fen_broc;   /* Total broadcast packet counter */
0586     uint    fen_mulc;   /* Total multicast packet count */
0587     uint    fen_uspc;   /* Total packets < 64 bytes */
0588     uint    fen_frgc;   /* Total packets < 64 bytes with errors */
0589     uint    fen_ospc;   /* Total packets > 1518 */
0590     uint    fen_jbrc;   /* Total packets > 1518 with errors */
0591     uint    fen_p64c;   /* Total packets == 64 bytes */
0592     uint    fen_p65c;   /* Total packets 64 < bytes <= 127 */
0593     uint    fen_p128c;  /* Total packets 127 < bytes <= 255 */
0594     uint    fen_p256c;  /* Total packets 256 < bytes <= 511 */
0595     uint    fen_p512c;  /* Total packets 512 < bytes <= 1023 */
0596     uint    fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
0597     uint    fen_cambuf; /* Internal CAM buffer pointer */
0598     ushort  fen_rfthr;  /* Received frames threshold */
0599     ushort  fen_rfcnt;  /* Received frames count */
0600 } fcc_enet_t;
0601 
0602 /* FCC Event/Mask register as used by Ethernet.
0603 */
0604 #define FCC_ENET_GRA    ((ushort)0x0080)    /* Graceful stop complete */
0605 #define FCC_ENET_RXC    ((ushort)0x0040)    /* Control Frame Received */
0606 #define FCC_ENET_TXC    ((ushort)0x0020)    /* Out of seq. Tx sent */
0607 #define FCC_ENET_TXE    ((ushort)0x0010)    /* Transmit Error */
0608 #define FCC_ENET_RXF    ((ushort)0x0008)    /* Full frame received */
0609 #define FCC_ENET_BSY    ((ushort)0x0004)    /* Busy.  Rx Frame dropped */
0610 #define FCC_ENET_TXB    ((ushort)0x0002)    /* A buffer was transmitted */
0611 #define FCC_ENET_RXB    ((ushort)0x0001)    /* A buffer was received */
0612 
0613 /* FCC Mode Register (FPSMR) as used by Ethernet.
0614 */
0615 #define FCC_PSMR_HBC    ((uint)0x80000000)  /* Enable heartbeat */
0616 #define FCC_PSMR_FC ((uint)0x40000000)  /* Force Collision */
0617 #define FCC_PSMR_SBT    ((uint)0x20000000)  /* Stop backoff timer */
0618 #define FCC_PSMR_LPB    ((uint)0x10000000)  /* Local protect. 1 = FDX */
0619 #define FCC_PSMR_LCW    ((uint)0x08000000)  /* Late collision select */
0620 #define FCC_PSMR_FDE    ((uint)0x04000000)  /* Full Duplex Enable */
0621 #define FCC_PSMR_MON    ((uint)0x02000000)  /* RMON Enable */
0622 #define FCC_PSMR_PRO    ((uint)0x00400000)  /* Promiscuous Enable */
0623 #define FCC_PSMR_FCE    ((uint)0x00200000)  /* Flow Control Enable */
0624 #define FCC_PSMR_RSH    ((uint)0x00100000)  /* Receive Short Frames */
0625 #define FCC_PSMR_CAM    ((uint)0x00000400)  /* CAM enable */
0626 #define FCC_PSMR_BRO    ((uint)0x00000200)  /* Broadcast pkt discard */
0627 #define FCC_PSMR_ENCRC  ((uint)0x00000080)  /* Use 32-bit CRC */
0628 
0629 /* IIC parameter RAM.
0630 */
0631 typedef struct iic {
0632     ushort  iic_rbase;  /* Rx Buffer descriptor base address */
0633     ushort  iic_tbase;  /* Tx Buffer descriptor base address */
0634     u_char  iic_rfcr;   /* Rx function code */
0635     u_char  iic_tfcr;   /* Tx function code */
0636     ushort  iic_mrblr;  /* Max receive buffer length */
0637     uint    iic_rstate; /* Internal */
0638     uint    iic_rdp;    /* Internal */
0639     ushort  iic_rbptr;  /* Internal */
0640     ushort  iic_rbc;    /* Internal */
0641     uint    iic_rxtmp;  /* Internal */
0642     uint    iic_tstate; /* Internal */
0643     uint    iic_tdp;    /* Internal */
0644     ushort  iic_tbptr;  /* Internal */
0645     ushort  iic_tbc;    /* Internal */
0646     uint    iic_txtmp;  /* Internal */
0647 } iic_t;
0648 
0649 /* IDMA parameter RAM
0650 */
0651 typedef struct idma {
0652     ushort ibase;       /* IDMA buffer descriptor table base address */
0653     ushort dcm;     /* DMA channel mode */
0654     ushort ibdptr;      /* IDMA current buffer descriptor pointer */
0655     ushort dpr_buf;     /* IDMA transfer buffer base address */
0656     ushort buf_inv;     /* internal buffer inventory */
0657     ushort ss_max;      /* steady-state maximum transfer size */
0658     ushort dpr_in_ptr;  /* write pointer inside the internal buffer */
0659     ushort sts;     /* source transfer size */
0660     ushort dpr_out_ptr; /* read pointer inside the internal buffer */
0661     ushort seob;        /* source end of burst */
0662     ushort deob;        /* destination end of burst */
0663     ushort dts;     /* destination transfer size */
0664     ushort ret_add;     /* return address when working in ERM=1 mode */
0665     ushort res0;        /* reserved */
0666     uint   bd_cnt;      /* internal byte count */
0667     uint   s_ptr;       /* source internal data pointer */
0668     uint   d_ptr;       /* destination internal data pointer */
0669     uint   istate;      /* internal state */
0670     u_char res1[20];    /* pad to 64-byte length */
0671 } idma_t;
0672 
0673 /* DMA channel mode bit fields
0674 */
0675 #define IDMA_DCM_FB     ((ushort)0x8000) /* fly-by mode */
0676 #define IDMA_DCM_LP     ((ushort)0x4000) /* low priority */
0677 #define IDMA_DCM_TC2        ((ushort)0x0400) /* value driven on TC[2] */
0678 #define IDMA_DCM_DMA_WRAP_MASK  ((ushort)0x01c0) /* mask for DMA wrap */
0679 #define IDMA_DCM_DMA_WRAP_64    ((ushort)0x0000) /* 64-byte DMA xfer buffer */
0680 #define IDMA_DCM_DMA_WRAP_128   ((ushort)0x0040) /* 128-byte DMA xfer buffer */
0681 #define IDMA_DCM_DMA_WRAP_256   ((ushort)0x0080) /* 256-byte DMA xfer buffer */
0682 #define IDMA_DCM_DMA_WRAP_512   ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
0683 #define IDMA_DCM_DMA_WRAP_1024  ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
0684 #define IDMA_DCM_DMA_WRAP_2048  ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
0685 #define IDMA_DCM_SINC       ((ushort)0x0020) /* source inc addr */
0686 #define IDMA_DCM_DINC       ((ushort)0x0010) /* destination inc addr */
0687 #define IDMA_DCM_ERM        ((ushort)0x0008) /* external request mode */
0688 #define IDMA_DCM_DT     ((ushort)0x0004) /* DONE treatment */
0689 #define IDMA_DCM_SD_MASK    ((ushort)0x0003) /* mask for SD bit field */
0690 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
0691 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
0692 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
0693 
0694 /* IDMA Buffer Descriptors
0695 */
0696 typedef struct idma_bd {
0697     uint flags;
0698     uint len;   /* data length */
0699     uint src;   /* source data buffer pointer */
0700     uint dst;   /* destination data buffer pointer */
0701 } idma_bd_t;
0702 
0703 /* IDMA buffer descriptor flag bit fields
0704 */
0705 #define IDMA_BD_V   ((uint)0x80000000)  /* valid */
0706 #define IDMA_BD_W   ((uint)0x20000000)  /* wrap */
0707 #define IDMA_BD_I   ((uint)0x10000000)  /* interrupt */
0708 #define IDMA_BD_L   ((uint)0x08000000)  /* last */
0709 #define IDMA_BD_CM  ((uint)0x02000000)  /* continuous mode */
0710 #define IDMA_BD_SDN ((uint)0x00400000)  /* source done */
0711 #define IDMA_BD_DDN ((uint)0x00200000)  /* destination done */
0712 #define IDMA_BD_DGBL    ((uint)0x00100000)  /* destination global */
0713 #define IDMA_BD_DBO_LE  ((uint)0x00040000)  /* little-end dest byte order */
0714 #define IDMA_BD_DBO_BE  ((uint)0x00080000)  /* big-end dest byte order */
0715 #define IDMA_BD_DDTB    ((uint)0x00010000)  /* destination data bus */
0716 #define IDMA_BD_SGBL    ((uint)0x00002000)  /* source global */
0717 #define IDMA_BD_SBO_LE  ((uint)0x00000800)  /* little-end src byte order */
0718 #define IDMA_BD_SBO_BE  ((uint)0x00001000)  /* big-end src byte order */
0719 #define IDMA_BD_SDTB    ((uint)0x00000200)  /* source data bus */
0720 
0721 /* per-channel IDMA registers
0722 */
0723 typedef struct im_idma {
0724     u_char idsr;            /* IDMAn event status register */
0725     u_char res0[3];
0726     u_char idmr;            /* IDMAn event mask register */
0727     u_char res1[3];
0728 } im_idma_t;
0729 
0730 /* IDMA event register bit fields
0731 */
0732 #define IDMA_EVENT_SC   ((unsigned char)0x08)   /* stop completed */
0733 #define IDMA_EVENT_OB   ((unsigned char)0x04)   /* out of buffers */
0734 #define IDMA_EVENT_EDN  ((unsigned char)0x02)   /* external DONE asserted */
0735 #define IDMA_EVENT_BC   ((unsigned char)0x01)   /* buffer descriptor complete */
0736 
0737 /* RISC Controller Configuration Register (RCCR) bit fields
0738 */
0739 #define RCCR_TIME   ((uint)0x80000000) /* timer enable */
0740 #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
0741 #define RCCR_DR0M   ((uint)0x00800000) /* IDMA0 request mode */
0742 #define RCCR_DR1M   ((uint)0x00400000) /* IDMA1 request mode */
0743 #define RCCR_DR2M   ((uint)0x00000080) /* IDMA2 request mode */
0744 #define RCCR_DR3M   ((uint)0x00000040) /* IDMA3 request mode */
0745 #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
0746 #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
0747 #define RCCR_DR0QP_MED  ((uint)0x00100000) /* IDMA0 has medium req priority */
0748 #define RCCR_DR0QP_LOW  ((uint)0x00200000) /* IDMA0 has low req priority */
0749 #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
0750 #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
0751 #define RCCR_DR1QP_MED  ((uint)0x00010000) /* IDMA1 has medium req priority */
0752 #define RCCR_DR1QP_LOW  ((uint)0x00020000) /* IDMA1 has low req priority */
0753 #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
0754 #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
0755 #define RCCR_DR2QP_MED  ((uint)0x00000010) /* IDMA2 has medium req priority */
0756 #define RCCR_DR2QP_LOW  ((uint)0x00000020) /* IDMA2 has low req priority */
0757 #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
0758 #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
0759 #define RCCR_DR3QP_MED  ((uint)0x00000001) /* IDMA3 has medium req priority */
0760 #define RCCR_DR3QP_LOW  ((uint)0x00000002) /* IDMA3 has low req priority */
0761 #define RCCR_EIE    ((uint)0x00080000) /* external interrupt enable */
0762 #define RCCR_SCD    ((uint)0x00040000) /* scheduler configuration */
0763 #define RCCR_ERAM_MASK  ((uint)0x0000e000) /* mask for enable RAM microcode */
0764 #define RCCR_ERAM_0KB   ((uint)0x00000000) /* use 0KB of dpram for microcode */
0765 #define RCCR_ERAM_2KB   ((uint)0x00002000) /* use 2KB of dpram for microcode */
0766 #define RCCR_ERAM_4KB   ((uint)0x00004000) /* use 4KB of dpram for microcode */
0767 #define RCCR_ERAM_6KB   ((uint)0x00006000) /* use 6KB of dpram for microcode */
0768 #define RCCR_ERAM_8KB   ((uint)0x00008000) /* use 8KB of dpram for microcode */
0769 #define RCCR_ERAM_10KB  ((uint)0x0000a000) /* use 10KB of dpram for microcode */
0770 #define RCCR_ERAM_12KB  ((uint)0x0000c000) /* use 12KB of dpram for microcode */
0771 #define RCCR_EDM0   ((uint)0x00000800) /* DREQ0 edge detect mode */
0772 #define RCCR_EDM1   ((uint)0x00000400) /* DREQ1 edge detect mode */
0773 #define RCCR_EDM2   ((uint)0x00000200) /* DREQ2 edge detect mode */
0774 #define RCCR_EDM3   ((uint)0x00000100) /* DREQ3 edge detect mode */
0775 #define RCCR_DEM01  ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
0776 #define RCCR_DEM23  ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
0777 
0778 /*-----------------------------------------------------------------------
0779  * CMXFCR - CMX FCC Clock Route Register
0780  */
0781 #define CMXFCR_FC1         0x40000000   /* FCC1 connection              */
0782 #define CMXFCR_RF1CS_MSK   0x38000000   /* Receive FCC1 Clock Source Mask */
0783 #define CMXFCR_TF1CS_MSK   0x07000000   /* Transmit FCC1 Clock Source Mask */
0784 #define CMXFCR_FC2         0x00400000   /* FCC2 connection              */
0785 #define CMXFCR_RF2CS_MSK   0x00380000   /* Receive FCC2 Clock Source Mask */
0786 #define CMXFCR_TF2CS_MSK   0x00070000   /* Transmit FCC2 Clock Source Mask */
0787 #define CMXFCR_FC3         0x00004000   /* FCC3 connection              */
0788 #define CMXFCR_RF3CS_MSK   0x00003800   /* Receive FCC3 Clock Source Mask */
0789 #define CMXFCR_TF3CS_MSK   0x00000700   /* Transmit FCC3 Clock Source Mask */
0790 
0791 #define CMXFCR_RF1CS_BRG5  0x00000000   /* Receive FCC1 Clock Source is BRG5 */
0792 #define CMXFCR_RF1CS_BRG6  0x08000000   /* Receive FCC1 Clock Source is BRG6 */
0793 #define CMXFCR_RF1CS_BRG7  0x10000000   /* Receive FCC1 Clock Source is BRG7 */
0794 #define CMXFCR_RF1CS_BRG8  0x18000000   /* Receive FCC1 Clock Source is BRG8 */
0795 #define CMXFCR_RF1CS_CLK9  0x20000000   /* Receive FCC1 Clock Source is CLK9 */
0796 #define CMXFCR_RF1CS_CLK10 0x28000000   /* Receive FCC1 Clock Source is CLK10 */
0797 #define CMXFCR_RF1CS_CLK11 0x30000000   /* Receive FCC1 Clock Source is CLK11 */
0798 #define CMXFCR_RF1CS_CLK12 0x38000000   /* Receive FCC1 Clock Source is CLK12 */
0799 
0800 #define CMXFCR_TF1CS_BRG5  0x00000000   /* Transmit FCC1 Clock Source is BRG5 */
0801 #define CMXFCR_TF1CS_BRG6  0x01000000   /* Transmit FCC1 Clock Source is BRG6 */
0802 #define CMXFCR_TF1CS_BRG7  0x02000000   /* Transmit FCC1 Clock Source is BRG7 */
0803 #define CMXFCR_TF1CS_BRG8  0x03000000   /* Transmit FCC1 Clock Source is BRG8 */
0804 #define CMXFCR_TF1CS_CLK9  0x04000000   /* Transmit FCC1 Clock Source is CLK9 */
0805 #define CMXFCR_TF1CS_CLK10 0x05000000   /* Transmit FCC1 Clock Source is CLK10 */
0806 #define CMXFCR_TF1CS_CLK11 0x06000000   /* Transmit FCC1 Clock Source is CLK11 */
0807 #define CMXFCR_TF1CS_CLK12 0x07000000   /* Transmit FCC1 Clock Source is CLK12 */
0808 
0809 #define CMXFCR_RF2CS_BRG5  0x00000000   /* Receive FCC2 Clock Source is BRG5 */
0810 #define CMXFCR_RF2CS_BRG6  0x00080000   /* Receive FCC2 Clock Source is BRG6 */
0811 #define CMXFCR_RF2CS_BRG7  0x00100000   /* Receive FCC2 Clock Source is BRG7 */
0812 #define CMXFCR_RF2CS_BRG8  0x00180000   /* Receive FCC2 Clock Source is BRG8 */
0813 #define CMXFCR_RF2CS_CLK13 0x00200000   /* Receive FCC2 Clock Source is CLK13 */
0814 #define CMXFCR_RF2CS_CLK14 0x00280000   /* Receive FCC2 Clock Source is CLK14 */
0815 #define CMXFCR_RF2CS_CLK15 0x00300000   /* Receive FCC2 Clock Source is CLK15 */
0816 #define CMXFCR_RF2CS_CLK16 0x00380000   /* Receive FCC2 Clock Source is CLK16 */
0817 
0818 #define CMXFCR_TF2CS_BRG5  0x00000000   /* Transmit FCC2 Clock Source is BRG5 */
0819 #define CMXFCR_TF2CS_BRG6  0x00010000   /* Transmit FCC2 Clock Source is BRG6 */
0820 #define CMXFCR_TF2CS_BRG7  0x00020000   /* Transmit FCC2 Clock Source is BRG7 */
0821 #define CMXFCR_TF2CS_BRG8  0x00030000   /* Transmit FCC2 Clock Source is BRG8 */
0822 #define CMXFCR_TF2CS_CLK13 0x00040000   /* Transmit FCC2 Clock Source is CLK13 */
0823 #define CMXFCR_TF2CS_CLK14 0x00050000   /* Transmit FCC2 Clock Source is CLK14 */
0824 #define CMXFCR_TF2CS_CLK15 0x00060000   /* Transmit FCC2 Clock Source is CLK15 */
0825 #define CMXFCR_TF2CS_CLK16 0x00070000   /* Transmit FCC2 Clock Source is CLK16 */
0826 
0827 #define CMXFCR_RF3CS_BRG5  0x00000000   /* Receive FCC3 Clock Source is BRG5 */
0828 #define CMXFCR_RF3CS_BRG6  0x00000800   /* Receive FCC3 Clock Source is BRG6 */
0829 #define CMXFCR_RF3CS_BRG7  0x00001000   /* Receive FCC3 Clock Source is BRG7 */
0830 #define CMXFCR_RF3CS_BRG8  0x00001800   /* Receive FCC3 Clock Source is BRG8 */
0831 #define CMXFCR_RF3CS_CLK13 0x00002000   /* Receive FCC3 Clock Source is CLK13 */
0832 #define CMXFCR_RF3CS_CLK14 0x00002800   /* Receive FCC3 Clock Source is CLK14 */
0833 #define CMXFCR_RF3CS_CLK15 0x00003000   /* Receive FCC3 Clock Source is CLK15 */
0834 #define CMXFCR_RF3CS_CLK16 0x00003800   /* Receive FCC3 Clock Source is CLK16 */
0835 
0836 #define CMXFCR_TF3CS_BRG5  0x00000000   /* Transmit FCC3 Clock Source is BRG5 */
0837 #define CMXFCR_TF3CS_BRG6  0x00000100   /* Transmit FCC3 Clock Source is BRG6 */
0838 #define CMXFCR_TF3CS_BRG7  0x00000200   /* Transmit FCC3 Clock Source is BRG7 */
0839 #define CMXFCR_TF3CS_BRG8  0x00000300   /* Transmit FCC3 Clock Source is BRG8 */
0840 #define CMXFCR_TF3CS_CLK13 0x00000400   /* Transmit FCC3 Clock Source is CLK13 */
0841 #define CMXFCR_TF3CS_CLK14 0x00000500   /* Transmit FCC3 Clock Source is CLK14 */
0842 #define CMXFCR_TF3CS_CLK15 0x00000600   /* Transmit FCC3 Clock Source is CLK15 */
0843 #define CMXFCR_TF3CS_CLK16 0x00000700   /* Transmit FCC3 Clock Source is CLK16 */
0844 
0845 /*-----------------------------------------------------------------------
0846  * CMXSCR - CMX SCC Clock Route Register
0847  */
0848 #define CMXSCR_GR1         0x80000000   /* Grant Support of SCC1        */
0849 #define CMXSCR_SC1         0x40000000   /* SCC1 connection              */
0850 #define CMXSCR_RS1CS_MSK   0x38000000   /* Receive SCC1 Clock Source Mask */
0851 #define CMXSCR_TS1CS_MSK   0x07000000   /* Transmit SCC1 Clock Source Mask */
0852 #define CMXSCR_GR2         0x00800000   /* Grant Support of SCC2        */
0853 #define CMXSCR_SC2         0x00400000   /* SCC2 connection              */
0854 #define CMXSCR_RS2CS_MSK   0x00380000   /* Receive SCC2 Clock Source Mask */
0855 #define CMXSCR_TS2CS_MSK   0x00070000   /* Transmit SCC2 Clock Source Mask */
0856 #define CMXSCR_GR3         0x00008000   /* Grant Support of SCC3        */
0857 #define CMXSCR_SC3         0x00004000   /* SCC3 connection              */
0858 #define CMXSCR_RS3CS_MSK   0x00003800   /* Receive SCC3 Clock Source Mask */
0859 #define CMXSCR_TS3CS_MSK   0x00000700   /* Transmit SCC3 Clock Source Mask */
0860 #define CMXSCR_GR4         0x00000080   /* Grant Support of SCC4        */
0861 #define CMXSCR_SC4         0x00000040   /* SCC4 connection              */
0862 #define CMXSCR_RS4CS_MSK   0x00000038   /* Receive SCC4 Clock Source Mask */
0863 #define CMXSCR_TS4CS_MSK   0x00000007   /* Transmit SCC4 Clock Source Mask */
0864 
0865 #define CMXSCR_RS1CS_BRG1  0x00000000   /* SCC1 Rx Clock Source is BRG1 */
0866 #define CMXSCR_RS1CS_BRG2  0x08000000   /* SCC1 Rx Clock Source is BRG2 */
0867 #define CMXSCR_RS1CS_BRG3  0x10000000   /* SCC1 Rx Clock Source is BRG3 */
0868 #define CMXSCR_RS1CS_BRG4  0x18000000   /* SCC1 Rx Clock Source is BRG4 */
0869 #define CMXSCR_RS1CS_CLK11 0x20000000   /* SCC1 Rx Clock Source is CLK11 */
0870 #define CMXSCR_RS1CS_CLK12 0x28000000   /* SCC1 Rx Clock Source is CLK12 */
0871 #define CMXSCR_RS1CS_CLK3  0x30000000   /* SCC1 Rx Clock Source is CLK3 */
0872 #define CMXSCR_RS1CS_CLK4  0x38000000   /* SCC1 Rx Clock Source is CLK4 */
0873 
0874 #define CMXSCR_TS1CS_BRG1  0x00000000   /* SCC1 Tx Clock Source is BRG1 */
0875 #define CMXSCR_TS1CS_BRG2  0x01000000   /* SCC1 Tx Clock Source is BRG2 */
0876 #define CMXSCR_TS1CS_BRG3  0x02000000   /* SCC1 Tx Clock Source is BRG3 */
0877 #define CMXSCR_TS1CS_BRG4  0x03000000   /* SCC1 Tx Clock Source is BRG4 */
0878 #define CMXSCR_TS1CS_CLK11 0x04000000   /* SCC1 Tx Clock Source is CLK11 */
0879 #define CMXSCR_TS1CS_CLK12 0x05000000   /* SCC1 Tx Clock Source is CLK12 */
0880 #define CMXSCR_TS1CS_CLK3  0x06000000   /* SCC1 Tx Clock Source is CLK3 */
0881 #define CMXSCR_TS1CS_CLK4  0x07000000   /* SCC1 Tx Clock Source is CLK4 */
0882 
0883 #define CMXSCR_RS2CS_BRG1  0x00000000   /* SCC2 Rx Clock Source is BRG1 */
0884 #define CMXSCR_RS2CS_BRG2  0x00080000   /* SCC2 Rx Clock Source is BRG2 */
0885 #define CMXSCR_RS2CS_BRG3  0x00100000   /* SCC2 Rx Clock Source is BRG3 */
0886 #define CMXSCR_RS2CS_BRG4  0x00180000   /* SCC2 Rx Clock Source is BRG4 */
0887 #define CMXSCR_RS2CS_CLK11 0x00200000   /* SCC2 Rx Clock Source is CLK11 */
0888 #define CMXSCR_RS2CS_CLK12 0x00280000   /* SCC2 Rx Clock Source is CLK12 */
0889 #define CMXSCR_RS2CS_CLK3  0x00300000   /* SCC2 Rx Clock Source is CLK3 */
0890 #define CMXSCR_RS2CS_CLK4  0x00380000   /* SCC2 Rx Clock Source is CLK4 */
0891 
0892 #define CMXSCR_TS2CS_BRG1  0x00000000   /* SCC2 Tx Clock Source is BRG1 */
0893 #define CMXSCR_TS2CS_BRG2  0x00010000   /* SCC2 Tx Clock Source is BRG2 */
0894 #define CMXSCR_TS2CS_BRG3  0x00020000   /* SCC2 Tx Clock Source is BRG3 */
0895 #define CMXSCR_TS2CS_BRG4  0x00030000   /* SCC2 Tx Clock Source is BRG4 */
0896 #define CMXSCR_TS2CS_CLK11 0x00040000   /* SCC2 Tx Clock Source is CLK11 */
0897 #define CMXSCR_TS2CS_CLK12 0x00050000   /* SCC2 Tx Clock Source is CLK12 */
0898 #define CMXSCR_TS2CS_CLK3  0x00060000   /* SCC2 Tx Clock Source is CLK3 */
0899 #define CMXSCR_TS2CS_CLK4  0x00070000   /* SCC2 Tx Clock Source is CLK4 */
0900 
0901 #define CMXSCR_RS3CS_BRG1  0x00000000   /* SCC3 Rx Clock Source is BRG1 */
0902 #define CMXSCR_RS3CS_BRG2  0x00000800   /* SCC3 Rx Clock Source is BRG2 */
0903 #define CMXSCR_RS3CS_BRG3  0x00001000   /* SCC3 Rx Clock Source is BRG3 */
0904 #define CMXSCR_RS3CS_BRG4  0x00001800   /* SCC3 Rx Clock Source is BRG4 */
0905 #define CMXSCR_RS3CS_CLK5  0x00002000   /* SCC3 Rx Clock Source is CLK5 */
0906 #define CMXSCR_RS3CS_CLK6  0x00002800   /* SCC3 Rx Clock Source is CLK6 */
0907 #define CMXSCR_RS3CS_CLK7  0x00003000   /* SCC3 Rx Clock Source is CLK7 */
0908 #define CMXSCR_RS3CS_CLK8  0x00003800   /* SCC3 Rx Clock Source is CLK8 */
0909 
0910 #define CMXSCR_TS3CS_BRG1  0x00000000   /* SCC3 Tx Clock Source is BRG1 */
0911 #define CMXSCR_TS3CS_BRG2  0x00000100   /* SCC3 Tx Clock Source is BRG2 */
0912 #define CMXSCR_TS3CS_BRG3  0x00000200   /* SCC3 Tx Clock Source is BRG3 */
0913 #define CMXSCR_TS3CS_BRG4  0x00000300   /* SCC3 Tx Clock Source is BRG4 */
0914 #define CMXSCR_TS3CS_CLK5  0x00000400   /* SCC3 Tx Clock Source is CLK5 */
0915 #define CMXSCR_TS3CS_CLK6  0x00000500   /* SCC3 Tx Clock Source is CLK6 */
0916 #define CMXSCR_TS3CS_CLK7  0x00000600   /* SCC3 Tx Clock Source is CLK7 */
0917 #define CMXSCR_TS3CS_CLK8  0x00000700   /* SCC3 Tx Clock Source is CLK8 */
0918 
0919 #define CMXSCR_RS4CS_BRG1  0x00000000   /* SCC4 Rx Clock Source is BRG1 */
0920 #define CMXSCR_RS4CS_BRG2  0x00000008   /* SCC4 Rx Clock Source is BRG2 */
0921 #define CMXSCR_RS4CS_BRG3  0x00000010   /* SCC4 Rx Clock Source is BRG3 */
0922 #define CMXSCR_RS4CS_BRG4  0x00000018   /* SCC4 Rx Clock Source is BRG4 */
0923 #define CMXSCR_RS4CS_CLK5  0x00000020   /* SCC4 Rx Clock Source is CLK5 */
0924 #define CMXSCR_RS4CS_CLK6  0x00000028   /* SCC4 Rx Clock Source is CLK6 */
0925 #define CMXSCR_RS4CS_CLK7  0x00000030   /* SCC4 Rx Clock Source is CLK7 */
0926 #define CMXSCR_RS4CS_CLK8  0x00000038   /* SCC4 Rx Clock Source is CLK8 */
0927 
0928 #define CMXSCR_TS4CS_BRG1  0x00000000   /* SCC4 Tx Clock Source is BRG1 */
0929 #define CMXSCR_TS4CS_BRG2  0x00000001   /* SCC4 Tx Clock Source is BRG2 */
0930 #define CMXSCR_TS4CS_BRG3  0x00000002   /* SCC4 Tx Clock Source is BRG3 */
0931 #define CMXSCR_TS4CS_BRG4  0x00000003   /* SCC4 Tx Clock Source is BRG4 */
0932 #define CMXSCR_TS4CS_CLK5  0x00000004   /* SCC4 Tx Clock Source is CLK5 */
0933 #define CMXSCR_TS4CS_CLK6  0x00000005   /* SCC4 Tx Clock Source is CLK6 */
0934 #define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
0935 #define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
0936 
0937 /*-----------------------------------------------------------------------
0938  * SIUMCR - SIU Module Configuration Register                4-31
0939  */
0940 #define SIUMCR_BBD  0x80000000  /* Bus Busy Disable     */
0941 #define SIUMCR_ESE  0x40000000  /* External Snoop Enable    */
0942 #define SIUMCR_PBSE 0x20000000  /* Parity Byte Select Enable    */
0943 #define SIUMCR_CDIS 0x10000000  /* Core Disable         */
0944 #define SIUMCR_DPPC00   0x00000000  /* Data Parity Pins Configuration*/
0945 #define SIUMCR_DPPC01   0x04000000  /* - " -            */
0946 #define SIUMCR_DPPC10   0x08000000  /* - " -            */
0947 #define SIUMCR_DPPC11   0x0c000000  /* - " -            */
0948 #define SIUMCR_L2CPC00  0x00000000  /* L2 Cache Pins Configuration  */
0949 #define SIUMCR_L2CPC01  0x01000000  /* - " -            */
0950 #define SIUMCR_L2CPC10  0x02000000  /* - " -            */
0951 #define SIUMCR_L2CPC11  0x03000000  /* - " -            */
0952 #define SIUMCR_LBPC00   0x00000000  /* Local Bus Pins Configuration */
0953 #define SIUMCR_LBPC01   0x00400000  /* - " -            */
0954 #define SIUMCR_LBPC10   0x00800000  /* - " -            */
0955 #define SIUMCR_LBPC11   0x00c00000  /* - " -            */
0956 #define SIUMCR_APPC00   0x00000000  /* Address Parity Pins Configuration*/
0957 #define SIUMCR_APPC01   0x00100000  /* - " -            */
0958 #define SIUMCR_APPC10   0x00200000  /* - " -            */
0959 #define SIUMCR_APPC11   0x00300000  /* - " -            */
0960 #define SIUMCR_CS10PC00 0x00000000  /* CS10 Pin Configuration   */
0961 #define SIUMCR_CS10PC01 0x00040000  /* - " -            */
0962 #define SIUMCR_CS10PC10 0x00080000  /* - " -            */
0963 #define SIUMCR_CS10PC11 0x000c0000  /* - " -            */
0964 #define SIUMCR_BCTLC00  0x00000000  /* Buffer Control Configuration */
0965 #define SIUMCR_BCTLC01  0x00010000  /* - " -            */
0966 #define SIUMCR_BCTLC10  0x00020000  /* - " -            */
0967 #define SIUMCR_BCTLC11  0x00030000  /* - " -            */
0968 #define SIUMCR_MMR00    0x00000000  /* Mask Masters Requests    */
0969 #define SIUMCR_MMR01    0x00004000  /* - " -            */
0970 #define SIUMCR_MMR10    0x00008000  /* - " -            */
0971 #define SIUMCR_MMR11    0x0000c000  /* - " -            */
0972 #define SIUMCR_LPBSE    0x00002000  /* LocalBus Parity Byte Select Enable*/
0973 
0974 /*-----------------------------------------------------------------------
0975  * SCCR - System Clock Control Register                  9-8
0976 */
0977 #define SCCR_PCI_MODE   0x00000100  /* PCI Mode */
0978 #define SCCR_PCI_MODCK  0x00000080  /* Value of PCI_MODCK pin   */
0979 #define SCCR_PCIDF_MSK  0x00000078  /* PCI division factor  */
0980 #define SCCR_PCIDF_SHIFT 3
0981 
0982 #ifndef CPM_IMMR_OFFSET
0983 #define CPM_IMMR_OFFSET 0x101a8
0984 #endif
0985 
0986 #define FCC_PSMR_RMII   ((uint)0x00020000)  /* Use RMII interface */
0987 
0988 /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
0989  * in order to use clock-computing stuff below for the FCC x
0990  */
0991 
0992 /* Automatically generates register configurations */
0993 #define PC_CLK(x)   ((uint)(1<<(x-1)))  /* FCC CLK I/O ports */
0994 
0995 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
0996 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
0997 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
0998 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
0999 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1000 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8))  /* FCC3 Transmit Clock Source */
1001 
1002 #define PC_F1RXCLK  PC_CLK(F1_RXCLK)
1003 #define PC_F1TXCLK  PC_CLK(F1_TXCLK)
1004 #define CMX1_CLK_ROUTE  (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1005 #define CMX1_CLK_MASK   ((uint)0xff000000)
1006 
1007 #define PC_F2RXCLK  PC_CLK(F2_RXCLK)
1008 #define PC_F2TXCLK  PC_CLK(F2_TXCLK)
1009 #define CMX2_CLK_ROUTE  (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1010 #define CMX2_CLK_MASK   ((uint)0x00ff0000)
1011 
1012 #define PC_F3RXCLK  PC_CLK(F3_RXCLK)
1013 #define PC_F3TXCLK  PC_CLK(F3_TXCLK)
1014 #define CMX3_CLK_ROUTE  (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1015 #define CMX3_CLK_MASK   ((uint)0x0000ff00)
1016 
1017 #define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1018 #define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1019 
1020 #define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1021 
1022 /* I/O Pin assignment for FCC1.  I don't yet know the best way to do this,
1023  * but there is little variation among the choices.
1024  */
1025 #define PA1_COL     0x00000001U
1026 #define PA1_CRS     0x00000002U
1027 #define PA1_TXER    0x00000004U
1028 #define PA1_TXEN    0x00000008U
1029 #define PA1_RXDV    0x00000010U
1030 #define PA1_RXER    0x00000020U
1031 #define PA1_TXDAT   0x00003c00U
1032 #define PA1_RXDAT   0x0003c000U
1033 #define PA1_PSORA0  (PA1_RXDAT | PA1_TXDAT)
1034 #define PA1_PSORA1  (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1035         PA1_RXDV | PA1_RXER)
1036 #define PA1_DIRA0   (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1037 #define PA1_DIRA1   (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1038 
1039 
1040 /* I/O Pin assignment for FCC2.  I don't yet know the best way to do this,
1041  * but there is little variation among the choices.
1042  */
1043 #define PB2_TXER    0x00000001U
1044 #define PB2_RXDV    0x00000002U
1045 #define PB2_TXEN    0x00000004U
1046 #define PB2_RXER    0x00000008U
1047 #define PB2_COL     0x00000010U
1048 #define PB2_CRS     0x00000020U
1049 #define PB2_TXDAT   0x000003c0U
1050 #define PB2_RXDAT   0x00003c00U
1051 #define PB2_PSORB0  (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1052         PB2_RXER | PB2_RXDV | PB2_TXER)
1053 #define PB2_PSORB1  (PB2_TXEN)
1054 #define PB2_DIRB0   (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1055 #define PB2_DIRB1   (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1056 
1057 
1058 /* I/O Pin assignment for FCC3.  I don't yet know the best way to do this,
1059  * but there is little variation among the choices.
1060  */
1061 #define PB3_RXDV    0x00004000U
1062 #define PB3_RXER    0x00008000U
1063 #define PB3_TXER    0x00010000U
1064 #define PB3_TXEN    0x00020000U
1065 #define PB3_COL     0x00040000U
1066 #define PB3_CRS     0x00080000U
1067 #define PB3_TXDAT   0x0f000000U
1068 #define PC3_TXDAT   0x00000010U
1069 #define PB3_RXDAT   0x00f00000U
1070 #define PB3_PSORB0  (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1071         PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1072 #define PB3_PSORB1  0
1073 #define PB3_DIRB0   (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1074 #define PB3_DIRB1   (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1075 #define PC3_DIRC1   (PC3_TXDAT)
1076 
1077 /* Handy macro to specify mem for FCCs*/
1078 #define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1079 #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1080 #define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1081 #define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1082 
1083 /* Clocks and GRG's */
1084 
1085 enum cpm_clk_dir {
1086     CPM_CLK_RX,
1087     CPM_CLK_TX,
1088     CPM_CLK_RTX
1089 };
1090 
1091 enum cpm_clk_target {
1092     CPM_CLK_SCC1,
1093     CPM_CLK_SCC2,
1094     CPM_CLK_SCC3,
1095     CPM_CLK_SCC4,
1096     CPM_CLK_FCC1,
1097     CPM_CLK_FCC2,
1098     CPM_CLK_FCC3,
1099     CPM_CLK_SMC1,
1100     CPM_CLK_SMC2,
1101 };
1102 
1103 enum cpm_clk {
1104     CPM_CLK_NONE = 0,
1105     CPM_BRG1,   /* Baud Rate Generator  1 */
1106     CPM_BRG2,   /* Baud Rate Generator  2 */
1107     CPM_BRG3,   /* Baud Rate Generator  3 */
1108     CPM_BRG4,   /* Baud Rate Generator  4 */
1109     CPM_BRG5,   /* Baud Rate Generator  5 */
1110     CPM_BRG6,   /* Baud Rate Generator  6 */
1111     CPM_BRG7,   /* Baud Rate Generator  7 */
1112     CPM_BRG8,   /* Baud Rate Generator  8 */
1113     CPM_CLK1,   /* Clock  1 */
1114     CPM_CLK2,   /* Clock  2 */
1115     CPM_CLK3,   /* Clock  3 */
1116     CPM_CLK4,   /* Clock  4 */
1117     CPM_CLK5,   /* Clock  5 */
1118     CPM_CLK6,   /* Clock  6 */
1119     CPM_CLK7,   /* Clock  7 */
1120     CPM_CLK8,   /* Clock  8 */
1121     CPM_CLK9,   /* Clock  9 */
1122     CPM_CLK10,  /* Clock 10 */
1123     CPM_CLK11,  /* Clock 11 */
1124     CPM_CLK12,  /* Clock 12 */
1125     CPM_CLK13,  /* Clock 13 */
1126     CPM_CLK14,  /* Clock 14 */
1127     CPM_CLK15,  /* Clock 15 */
1128     CPM_CLK16,  /* Clock 16 */
1129     CPM_CLK17,  /* Clock 17 */
1130     CPM_CLK18,  /* Clock 18 */
1131     CPM_CLK19,  /* Clock 19 */
1132     CPM_CLK20,  /* Clock 20 */
1133     CPM_CLK_DUMMY
1134 };
1135 
1136 int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1137 int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
1138 
1139 #define CPM_PIN_INPUT     0
1140 #define CPM_PIN_OUTPUT    1
1141 #define CPM_PIN_PRIMARY   0
1142 #define CPM_PIN_SECONDARY 2
1143 #define CPM_PIN_GPIO      4
1144 #define CPM_PIN_OPENDRAIN 8
1145 
1146 void __init cpm2_set_pin(int port, int pin, int flags);
1147 
1148 #endif /* __CPM2__ */
1149 #endif /* __KERNEL__ */
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