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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * MPC8xx Communication Processor Module.
0004  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
0005  *
0006  * This file contains structures and information for the communication
0007  * processor channels.  Some CPM control and status is available
0008  * through the MPC8xx internal memory map.  See immap.h for details.
0009  * This file only contains what I need for the moment, not the total
0010  * CPM capabilities.  I (or someone else) will add definitions as they
0011  * are needed.  -- Dan
0012  *
0013  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
0014  * bytes of the DP RAM and relocates the I2C parameter area to the
0015  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
0016  * or other use.
0017  */
0018 #ifndef __CPM1__
0019 #define __CPM1__
0020 
0021 #include <linux/init.h>
0022 #include <asm/8xx_immap.h>
0023 #include <asm/ptrace.h>
0024 #include <asm/cpm.h>
0025 
0026 /* CPM Command register.
0027 */
0028 #define CPM_CR_RST  ((ushort)0x8000)
0029 #define CPM_CR_OPCODE   ((ushort)0x0f00)
0030 #define CPM_CR_CHAN ((ushort)0x00f0)
0031 #define CPM_CR_FLG  ((ushort)0x0001)
0032 
0033 /* Channel numbers.
0034 */
0035 #define CPM_CR_CH_SCC1      ((ushort)0x0000)
0036 #define CPM_CR_CH_I2C       ((ushort)0x0001)    /* I2C and IDMA1 */
0037 #define CPM_CR_CH_SCC2      ((ushort)0x0004)
0038 #define CPM_CR_CH_SPI       ((ushort)0x0005)    /* SPI / IDMA2 / Timers */
0039 #define CPM_CR_CH_TIMER     CPM_CR_CH_SPI
0040 #define CPM_CR_CH_SCC3      ((ushort)0x0008)
0041 #define CPM_CR_CH_SMC1      ((ushort)0x0009)    /* SMC1 / DSP1 */
0042 #define CPM_CR_CH_SCC4      ((ushort)0x000c)
0043 #define CPM_CR_CH_SMC2      ((ushort)0x000d)    /* SMC2 / DSP2 */
0044 
0045 #define mk_cr_cmd(CH, CMD)  ((CMD << 8) | (CH << 4))
0046 
0047 /* Export the base address of the communication processor registers
0048  * and dual port ram.
0049  */
0050 extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
0051 
0052 #define cpm_dpalloc cpm_muram_alloc
0053 #define cpm_dpfree cpm_muram_free
0054 #define cpm_dpram_addr cpm_muram_addr
0055 #define cpm_dpram_phys cpm_muram_dma
0056 
0057 extern void cpm_setbrg(uint brg, uint rate);
0058 
0059 extern void __init cpm_load_patch(cpm8xx_t *cp);
0060 
0061 extern void cpm_reset(void);
0062 
0063 /* Parameter RAM offsets.
0064 */
0065 #define PROFF_SCC1  ((uint)0x0000)
0066 #define PROFF_IIC   ((uint)0x0080)
0067 #define PROFF_SCC2  ((uint)0x0100)
0068 #define PROFF_SPI   ((uint)0x0180)
0069 #define PROFF_SCC3  ((uint)0x0200)
0070 #define PROFF_SMC1  ((uint)0x0280)
0071 #define PROFF_DSP1  ((uint)0x02c0)
0072 #define PROFF_SCC4  ((uint)0x0300)
0073 #define PROFF_SMC2  ((uint)0x0380)
0074 
0075 /* Define enough so I can at least use the serial port as a UART.
0076  * The MBX uses SMC1 as the host serial port.
0077  */
0078 typedef struct smc_uart {
0079     ushort  smc_rbase;  /* Rx Buffer descriptor base address */
0080     ushort  smc_tbase;  /* Tx Buffer descriptor base address */
0081     u_char  smc_rfcr;   /* Rx function code */
0082     u_char  smc_tfcr;   /* Tx function code */
0083     ushort  smc_mrblr;  /* Max receive buffer length */
0084     uint    smc_rstate; /* Internal */
0085     uint    smc_idp;    /* Internal */
0086     ushort  smc_rbptr;  /* Internal */
0087     ushort  smc_ibc;    /* Internal */
0088     uint    smc_rxtmp;  /* Internal */
0089     uint    smc_tstate; /* Internal */
0090     uint    smc_tdp;    /* Internal */
0091     ushort  smc_tbptr;  /* Internal */
0092     ushort  smc_tbc;    /* Internal */
0093     uint    smc_txtmp;  /* Internal */
0094     ushort  smc_maxidl; /* Maximum idle characters */
0095     ushort  smc_tmpidl; /* Temporary idle counter */
0096     ushort  smc_brklen; /* Last received break length */
0097     ushort  smc_brkec;  /* rcv'd break condition counter */
0098     ushort  smc_brkcr;  /* xmt break count register */
0099     ushort  smc_rmask;  /* Temporary bit mask */
0100     char    res1[8];    /* Reserved */
0101     ushort  smc_rpbase; /* Relocation pointer */
0102 } smc_uart_t;
0103 
0104 /* Function code bits.
0105 */
0106 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
0107 
0108 /* SMC uart mode register.
0109 */
0110 #define SMCMR_REN   ((ushort)0x0001)
0111 #define SMCMR_TEN   ((ushort)0x0002)
0112 #define SMCMR_DM    ((ushort)0x000c)
0113 #define SMCMR_SM_GCI    ((ushort)0x0000)
0114 #define SMCMR_SM_UART   ((ushort)0x0020)
0115 #define SMCMR_SM_TRANS  ((ushort)0x0030)
0116 #define SMCMR_SM_MASK   ((ushort)0x0030)
0117 #define SMCMR_PM_EVEN   ((ushort)0x0100)    /* Even parity, else odd */
0118 #define SMCMR_REVD  SMCMR_PM_EVEN
0119 #define SMCMR_PEN   ((ushort)0x0200)    /* Parity enable */
0120 #define SMCMR_BS    SMCMR_PEN
0121 #define SMCMR_SL    ((ushort)0x0400)    /* Two stops, else one */
0122 #define SMCR_CLEN_MASK  ((ushort)0x7800)    /* Character length */
0123 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
0124 
0125 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
0126  * it can only receive or transmit.  The parameter ram values for
0127  * each direction are either unique or properly overlap, so we can
0128  * include them in one structure.
0129  */
0130 typedef struct smc_centronics {
0131     ushort  scent_rbase;
0132     ushort  scent_tbase;
0133     u_char  scent_cfcr;
0134     u_char  scent_smask;
0135     ushort  scent_mrblr;
0136     uint    scent_rstate;
0137     uint    scent_r_ptr;
0138     ushort  scent_rbptr;
0139     ushort  scent_r_cnt;
0140     uint    scent_rtemp;
0141     uint    scent_tstate;
0142     uint    scent_t_ptr;
0143     ushort  scent_tbptr;
0144     ushort  scent_t_cnt;
0145     uint    scent_ttemp;
0146     ushort  scent_max_sl;
0147     ushort  scent_sl_cnt;
0148     ushort  scent_character1;
0149     ushort  scent_character2;
0150     ushort  scent_character3;
0151     ushort  scent_character4;
0152     ushort  scent_character5;
0153     ushort  scent_character6;
0154     ushort  scent_character7;
0155     ushort  scent_character8;
0156     ushort  scent_rccm;
0157     ushort  scent_rccr;
0158 } smc_cent_t;
0159 
0160 /* Centronics Status Mask Register.
0161 */
0162 #define SMC_CENT_F  ((u_char)0x08)
0163 #define SMC_CENT_PE ((u_char)0x04)
0164 #define SMC_CENT_S  ((u_char)0x02)
0165 
0166 /* SMC Event and Mask register.
0167 */
0168 #define SMCM_BRKE   ((unsigned char)0x40)   /* When in UART Mode */
0169 #define SMCM_BRK    ((unsigned char)0x10)   /* When in UART Mode */
0170 #define SMCM_TXE    ((unsigned char)0x10)   /* When in Transparent Mode */
0171 #define SMCM_BSY    ((unsigned char)0x04)
0172 #define SMCM_TX     ((unsigned char)0x02)
0173 #define SMCM_RX     ((unsigned char)0x01)
0174 
0175 /* Baud rate generators.
0176 */
0177 #define CPM_BRG_RST     ((uint)0x00020000)
0178 #define CPM_BRG_EN      ((uint)0x00010000)
0179 #define CPM_BRG_EXTC_INT    ((uint)0x00000000)
0180 #define CPM_BRG_EXTC_CLK2   ((uint)0x00004000)
0181 #define CPM_BRG_EXTC_CLK6   ((uint)0x00008000)
0182 #define CPM_BRG_ATB     ((uint)0x00002000)
0183 #define CPM_BRG_CD_MASK     ((uint)0x00001ffe)
0184 #define CPM_BRG_DIV16       ((uint)0x00000001)
0185 
0186 /* SI Clock Route Register
0187 */
0188 #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
0189 #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
0190 #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
0191 #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
0192 #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
0193 #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
0194 #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
0195 #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
0196 
0197 /* SCCs.
0198 */
0199 #define SCC_GSMRH_IRP       ((uint)0x00040000)
0200 #define SCC_GSMRH_GDE       ((uint)0x00010000)
0201 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
0202 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
0203 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
0204 #define SCC_GSMRH_REVD      ((uint)0x00002000)
0205 #define SCC_GSMRH_TRX       ((uint)0x00001000)
0206 #define SCC_GSMRH_TTX       ((uint)0x00000800)
0207 #define SCC_GSMRH_CDP       ((uint)0x00000400)
0208 #define SCC_GSMRH_CTSP      ((uint)0x00000200)
0209 #define SCC_GSMRH_CDS       ((uint)0x00000100)
0210 #define SCC_GSMRH_CTSS      ((uint)0x00000080)
0211 #define SCC_GSMRH_TFL       ((uint)0x00000040)
0212 #define SCC_GSMRH_RFW       ((uint)0x00000020)
0213 #define SCC_GSMRH_TXSY      ((uint)0x00000010)
0214 #define SCC_GSMRH_SYNL16    ((uint)0x0000000c)
0215 #define SCC_GSMRH_SYNL8     ((uint)0x00000008)
0216 #define SCC_GSMRH_SYNL4     ((uint)0x00000004)
0217 #define SCC_GSMRH_RTSM      ((uint)0x00000002)
0218 #define SCC_GSMRH_RSYN      ((uint)0x00000001)
0219 
0220 #define SCC_GSMRL_SIR       ((uint)0x80000000)  /* SCC2 only */
0221 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
0222 #define SCC_GSMRL_EDGE_NEG  ((uint)0x40000000)
0223 #define SCC_GSMRL_EDGE_POS  ((uint)0x20000000)
0224 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
0225 #define SCC_GSMRL_TCI       ((uint)0x10000000)
0226 #define SCC_GSMRL_TSNC_3    ((uint)0x0c000000)
0227 #define SCC_GSMRL_TSNC_4    ((uint)0x08000000)
0228 #define SCC_GSMRL_TSNC_14   ((uint)0x04000000)
0229 #define SCC_GSMRL_TSNC_INF  ((uint)0x00000000)
0230 #define SCC_GSMRL_RINV      ((uint)0x02000000)
0231 #define SCC_GSMRL_TINV      ((uint)0x01000000)
0232 #define SCC_GSMRL_TPL_128   ((uint)0x00c00000)
0233 #define SCC_GSMRL_TPL_64    ((uint)0x00a00000)
0234 #define SCC_GSMRL_TPL_48    ((uint)0x00800000)
0235 #define SCC_GSMRL_TPL_32    ((uint)0x00600000)
0236 #define SCC_GSMRL_TPL_16    ((uint)0x00400000)
0237 #define SCC_GSMRL_TPL_8     ((uint)0x00200000)
0238 #define SCC_GSMRL_TPL_NONE  ((uint)0x00000000)
0239 #define SCC_GSMRL_TPP_ALL1  ((uint)0x00180000)
0240 #define SCC_GSMRL_TPP_01    ((uint)0x00100000)
0241 #define SCC_GSMRL_TPP_10    ((uint)0x00080000)
0242 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
0243 #define SCC_GSMRL_TEND      ((uint)0x00040000)
0244 #define SCC_GSMRL_TDCR_32   ((uint)0x00030000)
0245 #define SCC_GSMRL_TDCR_16   ((uint)0x00020000)
0246 #define SCC_GSMRL_TDCR_8    ((uint)0x00010000)
0247 #define SCC_GSMRL_TDCR_1    ((uint)0x00000000)
0248 #define SCC_GSMRL_RDCR_32   ((uint)0x0000c000)
0249 #define SCC_GSMRL_RDCR_16   ((uint)0x00008000)
0250 #define SCC_GSMRL_RDCR_8    ((uint)0x00004000)
0251 #define SCC_GSMRL_RDCR_1    ((uint)0x00000000)
0252 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
0253 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
0254 #define SCC_GSMRL_RENC_FM0  ((uint)0x00001000)
0255 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
0256 #define SCC_GSMRL_RENC_NRZ  ((uint)0x00000000)
0257 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
0258 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
0259 #define SCC_GSMRL_TENC_FM0  ((uint)0x00000200)
0260 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
0261 #define SCC_GSMRL_TENC_NRZ  ((uint)0x00000000)
0262 #define SCC_GSMRL_DIAG_LE   ((uint)0x000000c0)  /* Loop and echo */
0263 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
0264 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
0265 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
0266 #define SCC_GSMRL_ENR       ((uint)0x00000020)
0267 #define SCC_GSMRL_ENT       ((uint)0x00000010)
0268 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
0269 #define SCC_GSMRL_MODE_QMC  ((uint)0x0000000a)
0270 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
0271 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
0272 #define SCC_GSMRL_MODE_V14  ((uint)0x00000007)
0273 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
0274 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
0275 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
0276 #define SCC_GSMRL_MODE_SS7  ((uint)0x00000003)
0277 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
0278 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
0279 
0280 #define SCC_TODR_TOD        ((ushort)0x8000)
0281 
0282 /* SCC Event and Mask register.
0283 */
0284 #define SCCM_TXE    ((unsigned char)0x10)
0285 #define SCCM_BSY    ((unsigned char)0x04)
0286 #define SCCM_TX     ((unsigned char)0x02)
0287 #define SCCM_RX     ((unsigned char)0x01)
0288 
0289 typedef struct scc_param {
0290     ushort  scc_rbase;  /* Rx Buffer descriptor base address */
0291     ushort  scc_tbase;  /* Tx Buffer descriptor base address */
0292     u_char  scc_rfcr;   /* Rx function code */
0293     u_char  scc_tfcr;   /* Tx function code */
0294     ushort  scc_mrblr;  /* Max receive buffer length */
0295     uint    scc_rstate; /* Internal */
0296     uint    scc_idp;    /* Internal */
0297     ushort  scc_rbptr;  /* Internal */
0298     ushort  scc_ibc;    /* Internal */
0299     uint    scc_rxtmp;  /* Internal */
0300     uint    scc_tstate; /* Internal */
0301     uint    scc_tdp;    /* Internal */
0302     ushort  scc_tbptr;  /* Internal */
0303     ushort  scc_tbc;    /* Internal */
0304     uint    scc_txtmp;  /* Internal */
0305     uint    scc_rcrc;   /* Internal */
0306     uint    scc_tcrc;   /* Internal */
0307 } sccp_t;
0308 
0309 /* Function code bits.
0310 */
0311 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
0312 
0313 /* CPM Ethernet through SCCx.
0314  */
0315 typedef struct scc_enet {
0316     sccp_t  sen_genscc;
0317     uint    sen_cpres;  /* Preset CRC */
0318     uint    sen_cmask;  /* Constant mask for CRC */
0319     uint    sen_crcec;  /* CRC Error counter */
0320     uint    sen_alec;   /* alignment error counter */
0321     uint    sen_disfc;  /* discard frame counter */
0322     ushort  sen_pads;   /* Tx short frame pad character */
0323     ushort  sen_retlim; /* Retry limit threshold */
0324     ushort  sen_retcnt; /* Retry limit counter */
0325     ushort  sen_maxflr; /* maximum frame length register */
0326     ushort  sen_minflr; /* minimum frame length register */
0327     ushort  sen_maxd1;  /* maximum DMA1 length */
0328     ushort  sen_maxd2;  /* maximum DMA2 length */
0329     ushort  sen_maxd;   /* Rx max DMA */
0330     ushort  sen_dmacnt; /* Rx DMA counter */
0331     ushort  sen_maxb;   /* Max BD byte count */
0332     ushort  sen_gaddr1; /* Group address filter */
0333     ushort  sen_gaddr2;
0334     ushort  sen_gaddr3;
0335     ushort  sen_gaddr4;
0336     uint    sen_tbuf0data0; /* Save area 0 - current frame */
0337     uint    sen_tbuf0data1; /* Save area 1 - current frame */
0338     uint    sen_tbuf0rba;   /* Internal */
0339     uint    sen_tbuf0crc;   /* Internal */
0340     ushort  sen_tbuf0bcnt;  /* Internal */
0341     ushort  sen_paddrh; /* physical address (MSB) */
0342     ushort  sen_paddrm;
0343     ushort  sen_paddrl; /* physical address (LSB) */
0344     ushort  sen_pper;   /* persistence */
0345     ushort  sen_rfbdptr;    /* Rx first BD pointer */
0346     ushort  sen_tfbdptr;    /* Tx first BD pointer */
0347     ushort  sen_tlbdptr;    /* Tx last BD pointer */
0348     uint    sen_tbuf1data0; /* Save area 0 - current frame */
0349     uint    sen_tbuf1data1; /* Save area 1 - current frame */
0350     uint    sen_tbuf1rba;   /* Internal */
0351     uint    sen_tbuf1crc;   /* Internal */
0352     ushort  sen_tbuf1bcnt;  /* Internal */
0353     ushort  sen_txlen;  /* Tx Frame length counter */
0354     ushort  sen_iaddr1; /* Individual address filter */
0355     ushort  sen_iaddr2;
0356     ushort  sen_iaddr3;
0357     ushort  sen_iaddr4;
0358     ushort  sen_boffcnt;    /* Backoff counter */
0359 
0360     /* NOTE: Some versions of the manual have the following items
0361      * incorrectly documented.  Below is the proper order.
0362      */
0363     ushort  sen_taddrh; /* temp address (MSB) */
0364     ushort  sen_taddrm;
0365     ushort  sen_taddrl; /* temp address (LSB) */
0366 } scc_enet_t;
0367 
0368 /* SCC Event register as used by Ethernet.
0369 */
0370 #define SCCE_ENET_GRA   ((ushort)0x0080)    /* Graceful stop complete */
0371 #define SCCE_ENET_TXE   ((ushort)0x0010)    /* Transmit Error */
0372 #define SCCE_ENET_RXF   ((ushort)0x0008)    /* Full frame received */
0373 #define SCCE_ENET_BSY   ((ushort)0x0004)    /* All incoming buffers full */
0374 #define SCCE_ENET_TXB   ((ushort)0x0002)    /* A buffer was transmitted */
0375 #define SCCE_ENET_RXB   ((ushort)0x0001)    /* A buffer was received */
0376 
0377 /* SCC Mode Register (PMSR) as used by Ethernet.
0378 */
0379 #define SCC_PSMR_HBC    ((ushort)0x8000)    /* Enable heartbeat */
0380 #define SCC_PSMR_FC ((ushort)0x4000)    /* Force collision */
0381 #define SCC_PSMR_RSH    ((ushort)0x2000)    /* Receive short frames */
0382 #define SCC_PSMR_IAM    ((ushort)0x1000)    /* Check individual hash */
0383 #define SCC_PSMR_ENCRC  ((ushort)0x0800)    /* Ethernet CRC mode */
0384 #define SCC_PSMR_PRO    ((ushort)0x0200)    /* Promiscuous mode */
0385 #define SCC_PSMR_BRO    ((ushort)0x0100)    /* Catch broadcast pkts */
0386 #define SCC_PSMR_SBT    ((ushort)0x0080)    /* Special backoff timer */
0387 #define SCC_PSMR_LPB    ((ushort)0x0040)    /* Set Loopback mode */
0388 #define SCC_PSMR_SIP    ((ushort)0x0020)    /* Sample Input Pins */
0389 #define SCC_PSMR_LCW    ((ushort)0x0010)    /* Late collision window */
0390 #define SCC_PSMR_NIB22  ((ushort)0x000a)    /* Start frame search */
0391 #define SCC_PSMR_FDE    ((ushort)0x0001)    /* Full duplex enable */
0392 
0393 /* SCC as UART
0394 */
0395 typedef struct scc_uart {
0396     sccp_t  scc_genscc;
0397     char    res1[8];    /* Reserved */
0398     ushort  scc_maxidl; /* Maximum idle chars */
0399     ushort  scc_idlc;   /* temp idle counter */
0400     ushort  scc_brkcr;  /* Break count register */
0401     ushort  scc_parec;  /* receive parity error counter */
0402     ushort  scc_frmec;  /* receive framing error counter */
0403     ushort  scc_nosec;  /* receive noise counter */
0404     ushort  scc_brkec;  /* receive break condition counter */
0405     ushort  scc_brkln;  /* last received break length */
0406     ushort  scc_uaddr1; /* UART address character 1 */
0407     ushort  scc_uaddr2; /* UART address character 2 */
0408     ushort  scc_rtemp;  /* Temp storage */
0409     ushort  scc_toseq;  /* Transmit out of sequence char */
0410     ushort  scc_char1;  /* control character 1 */
0411     ushort  scc_char2;  /* control character 2 */
0412     ushort  scc_char3;  /* control character 3 */
0413     ushort  scc_char4;  /* control character 4 */
0414     ushort  scc_char5;  /* control character 5 */
0415     ushort  scc_char6;  /* control character 6 */
0416     ushort  scc_char7;  /* control character 7 */
0417     ushort  scc_char8;  /* control character 8 */
0418     ushort  scc_rccm;   /* receive control character mask */
0419     ushort  scc_rccr;   /* receive control character register */
0420     ushort  scc_rlbc;   /* receive last break character */
0421 } scc_uart_t;
0422 
0423 /* SCC Event and Mask registers when it is used as a UART.
0424 */
0425 #define UART_SCCM_GLR       ((ushort)0x1000)
0426 #define UART_SCCM_GLT       ((ushort)0x0800)
0427 #define UART_SCCM_AB        ((ushort)0x0200)
0428 #define UART_SCCM_IDL       ((ushort)0x0100)
0429 #define UART_SCCM_GRA       ((ushort)0x0080)
0430 #define UART_SCCM_BRKE      ((ushort)0x0040)
0431 #define UART_SCCM_BRKS      ((ushort)0x0020)
0432 #define UART_SCCM_CCR       ((ushort)0x0008)
0433 #define UART_SCCM_BSY       ((ushort)0x0004)
0434 #define UART_SCCM_TX        ((ushort)0x0002)
0435 #define UART_SCCM_RX        ((ushort)0x0001)
0436 
0437 /* The SCC PMSR when used as a UART.
0438 */
0439 #define SCU_PSMR_FLC        ((ushort)0x8000)
0440 #define SCU_PSMR_SL     ((ushort)0x4000)
0441 #define SCU_PSMR_CL     ((ushort)0x3000)
0442 #define SCU_PSMR_UM     ((ushort)0x0c00)
0443 #define SCU_PSMR_FRZ        ((ushort)0x0200)
0444 #define SCU_PSMR_RZS        ((ushort)0x0100)
0445 #define SCU_PSMR_SYN        ((ushort)0x0080)
0446 #define SCU_PSMR_DRT        ((ushort)0x0040)
0447 #define SCU_PSMR_PEN        ((ushort)0x0010)
0448 #define SCU_PSMR_RPM        ((ushort)0x000c)
0449 #define SCU_PSMR_REVP       ((ushort)0x0008)
0450 #define SCU_PSMR_TPM        ((ushort)0x0003)
0451 #define SCU_PSMR_TEVP       ((ushort)0x0002)
0452 
0453 /* CPM Transparent mode SCC.
0454  */
0455 typedef struct scc_trans {
0456     sccp_t  st_genscc;
0457     uint    st_cpres;   /* Preset CRC */
0458     uint    st_cmask;   /* Constant mask for CRC */
0459 } scc_trans_t;
0460 
0461 /* IIC parameter RAM.
0462 */
0463 typedef struct iic {
0464     ushort  iic_rbase;  /* Rx Buffer descriptor base address */
0465     ushort  iic_tbase;  /* Tx Buffer descriptor base address */
0466     u_char  iic_rfcr;   /* Rx function code */
0467     u_char  iic_tfcr;   /* Tx function code */
0468     ushort  iic_mrblr;  /* Max receive buffer length */
0469     uint    iic_rstate; /* Internal */
0470     uint    iic_rdp;    /* Internal */
0471     ushort  iic_rbptr;  /* Internal */
0472     ushort  iic_rbc;    /* Internal */
0473     uint    iic_rxtmp;  /* Internal */
0474     uint    iic_tstate; /* Internal */
0475     uint    iic_tdp;    /* Internal */
0476     ushort  iic_tbptr;  /* Internal */
0477     ushort  iic_tbc;    /* Internal */
0478     uint    iic_txtmp;  /* Internal */
0479     char    res1[4];    /* Reserved */
0480     ushort  iic_rpbase; /* Relocation pointer */
0481     char    res2[2];    /* Reserved */
0482 } iic_t;
0483 
0484 /*
0485  * RISC Controller Configuration Register definitons
0486  */
0487 #define RCCR_TIME   0x8000          /* RISC Timer Enable */
0488 #define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)   /* RISC Timer Period */
0489 #define RCCR_TIME_MASK  0x00FF          /* not RISC Timer related bits */
0490 
0491 /* RISC Timer Parameter RAM offset */
0492 #define PROFF_RTMR  ((uint)0x01B0)
0493 
0494 typedef struct risc_timer_pram {
0495     unsigned short  tm_base;    /* RISC Timer Table Base Address */
0496     unsigned short  tm_ptr;     /* RISC Timer Table Pointer (internal) */
0497     unsigned short  r_tmr;      /* RISC Timer Mode Register */
0498     unsigned short  r_tmv;      /* RISC Timer Valid Register */
0499     unsigned long   tm_cmd;     /* RISC Timer Command Register */
0500     unsigned long   tm_cnt;     /* RISC Timer Internal Count */
0501 } rt_pram_t;
0502 
0503 /* Bits in RISC Timer Command Register */
0504 #define TM_CMD_VALID    0x80000000  /* Valid - Enables the timer */
0505 #define TM_CMD_RESTART  0x40000000  /* Restart - for automatic restart */
0506 #define TM_CMD_PWM  0x20000000  /* Run in Pulse Width Modulation Mode */
0507 #define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
0508 #define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
0509 
0510 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
0511  * channels or devices.  All of these are presented to the PPC core
0512  * as a single interrupt.  The CPM interrupt handler dispatches its
0513  * own handlers, in a similar fashion to the PPC core handler.  We
0514  * use the table as defined in the manuals (i.e. no special high
0515  * priority and SCC1 == SCCa, etc...).
0516  */
0517 #define CPMVEC_NR       32
0518 #define CPMVEC_PIO_PC15     ((ushort)0x1f)
0519 #define CPMVEC_SCC1     ((ushort)0x1e)
0520 #define CPMVEC_SCC2     ((ushort)0x1d)
0521 #define CPMVEC_SCC3     ((ushort)0x1c)
0522 #define CPMVEC_SCC4     ((ushort)0x1b)
0523 #define CPMVEC_PIO_PC14     ((ushort)0x1a)
0524 #define CPMVEC_TIMER1       ((ushort)0x19)
0525 #define CPMVEC_PIO_PC13     ((ushort)0x18)
0526 #define CPMVEC_PIO_PC12     ((ushort)0x17)
0527 #define CPMVEC_SDMA_CB_ERR  ((ushort)0x16)
0528 #define CPMVEC_IDMA1        ((ushort)0x15)
0529 #define CPMVEC_IDMA2        ((ushort)0x14)
0530 #define CPMVEC_TIMER2       ((ushort)0x12)
0531 #define CPMVEC_RISCTIMER    ((ushort)0x11)
0532 #define CPMVEC_I2C      ((ushort)0x10)
0533 #define CPMVEC_PIO_PC11     ((ushort)0x0f)
0534 #define CPMVEC_PIO_PC10     ((ushort)0x0e)
0535 #define CPMVEC_TIMER3       ((ushort)0x0c)
0536 #define CPMVEC_PIO_PC9      ((ushort)0x0b)
0537 #define CPMVEC_PIO_PC8      ((ushort)0x0a)
0538 #define CPMVEC_PIO_PC7      ((ushort)0x09)
0539 #define CPMVEC_TIMER4       ((ushort)0x07)
0540 #define CPMVEC_PIO_PC6      ((ushort)0x06)
0541 #define CPMVEC_SPI      ((ushort)0x05)
0542 #define CPMVEC_SMC1     ((ushort)0x04)
0543 #define CPMVEC_SMC2     ((ushort)0x03)
0544 #define CPMVEC_PIO_PC5      ((ushort)0x02)
0545 #define CPMVEC_PIO_PC4      ((ushort)0x01)
0546 #define CPMVEC_ERROR        ((ushort)0x00)
0547 
0548 /* CPM interrupt configuration vector.
0549 */
0550 #define CICR_SCD_SCC4       ((uint)0x00c00000)  /* SCC4 @ SCCd */
0551 #define CICR_SCC_SCC3       ((uint)0x00200000)  /* SCC3 @ SCCc */
0552 #define CICR_SCB_SCC2       ((uint)0x00040000)  /* SCC2 @ SCCb */
0553 #define CICR_SCA_SCC1       ((uint)0x00000000)  /* SCC1 @ SCCa */
0554 #define CICR_IRL_MASK       ((uint)0x0000e000)  /* Core interrupt */
0555 #define CICR_HP_MASK        ((uint)0x00001f00)  /* Hi-pri int. */
0556 #define CICR_IEN        ((uint)0x00000080)  /* Int. enable */
0557 #define CICR_SPS        ((uint)0x00000001)  /* SCC Spread */
0558 
0559 #define CPM_PIN_INPUT     0
0560 #define CPM_PIN_OUTPUT    1
0561 #define CPM_PIN_PRIMARY   0
0562 #define CPM_PIN_SECONDARY 2
0563 #define CPM_PIN_GPIO      4
0564 #define CPM_PIN_OPENDRAIN 8
0565 #define CPM_PIN_FALLEDGE  16
0566 #define CPM_PIN_ANYEDGE   0
0567 
0568 enum cpm_port {
0569     CPM_PORTA,
0570     CPM_PORTB,
0571     CPM_PORTC,
0572     CPM_PORTD,
0573     CPM_PORTE,
0574 };
0575 
0576 void cpm1_set_pin(enum cpm_port port, int pin, int flags);
0577 
0578 enum cpm_clk_dir {
0579     CPM_CLK_RX,
0580     CPM_CLK_TX,
0581     CPM_CLK_RTX
0582 };
0583 
0584 enum cpm_clk_target {
0585     CPM_CLK_SCC1,
0586     CPM_CLK_SCC2,
0587     CPM_CLK_SCC3,
0588     CPM_CLK_SCC4,
0589     CPM_CLK_SMC1,
0590     CPM_CLK_SMC2,
0591 };
0592 
0593 enum cpm_clk {
0594     CPM_BRG1,   /* Baud Rate Generator  1 */
0595     CPM_BRG2,   /* Baud Rate Generator  2 */
0596     CPM_BRG3,   /* Baud Rate Generator  3 */
0597     CPM_BRG4,   /* Baud Rate Generator  4 */
0598     CPM_CLK1,   /* Clock  1 */
0599     CPM_CLK2,   /* Clock  2 */
0600     CPM_CLK3,   /* Clock  3 */
0601     CPM_CLK4,   /* Clock  4 */
0602     CPM_CLK5,   /* Clock  5 */
0603     CPM_CLK6,   /* Clock  6 */
0604     CPM_CLK7,   /* Clock  7 */
0605     CPM_CLK8,   /* Clock  8 */
0606 };
0607 
0608 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
0609 int cpm1_gpiochip_add16(struct device *dev);
0610 int cpm1_gpiochip_add32(struct device *dev);
0611 
0612 #endif /* __CPM1__ */
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