include/asm/cell-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * cbe_regs.h
0004  *
0005  * This file is intended to hold the various register definitions for CBE
0006  * on-chip system devices (memory controller, IO controller, etc...)
0007  *
0008  * (C) Copyright IBM Corporation 2001,2006
0009  *
0010  * Authors: Maximino Aguilar (maguilar@us.ibm.com)
0011  *          David J. Erb (djerb@us.ibm.com)
0012  *
0013  * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
0014  */
0015
0016 #ifndef CBE_REGS_H
0017 #define CBE_REGS_H
0018
0019 #include <asm/cell-pmu.h>
0020
0021 /*
0022  *
0023  * Some HID register definitions
0024  *
0025  */
0026
0027 /* CBE specific HID0 bits */
0028 #define HID0_CBE_THERM_WAKEUP   0x0000020000000000ul
0029 #define HID0_CBE_SYSERR_WAKEUP  0x0000008000000000ul
0030 #define HID0_CBE_THERM_INT_EN   0x0000000400000000ul
0031 #define HID0_CBE_SYSERR_INT_EN  0x0000000200000000ul
0032
0033 #define MAX_CBE     2
0034
0035 /*
0036  *
0037  * Pervasive unit register definitions
0038  *
0039  */
0040
0041 union spe_reg {
0042     u64 val;
0043     u8 spe[8];
0044 };
0045
0046 union ppe_spe_reg {
0047     u64 val;
0048     struct {
0049         u32 ppe;
0050         u32 spe;
0051     };
0052 };
0053
0054
0055 struct cbe_pmd_regs {
0056     /* Debug Bus Control */
0057     u64 pad_0x0000;                 /* 0x0000 */
0058
0059     u64 group_control;                  /* 0x0008 */
0060
0061     u8  pad_0x0010_0x00a8 [0x00a8 - 0x0010];        /* 0x0010 */
0062
0063     u64 debug_bus_control;              /* 0x00a8 */
0064
0065     u8  pad_0x00b0_0x0100 [0x0100 - 0x00b0];        /* 0x00b0 */
0066
0067     u64 trace_aux_data;                 /* 0x0100 */
0068     u64 trace_buffer_0_63;              /* 0x0108 */
0069     u64 trace_buffer_64_127;                /* 0x0110 */
0070     u64 trace_address;                  /* 0x0118 */
0071     u64 ext_tr_timer;                   /* 0x0120 */
0072
0073     u8  pad_0x0128_0x0400 [0x0400 - 0x0128];        /* 0x0128 */
0074
0075     /* Performance Monitor */
0076     u64 pm_status;                  /* 0x0400 */
0077     u64 pm_control;                 /* 0x0408 */
0078     u64 pm_interval;                    /* 0x0410 */
0079     u64 pm_ctr[4];                  /* 0x0418 */
0080     u64 pm_start_stop;                  /* 0x0438 */
0081     u64 pm07_control[8];                /* 0x0440 */
0082
0083     u8  pad_0x0480_0x0800 [0x0800 - 0x0480];        /* 0x0480 */
0084
0085     /* Thermal Sensor Registers */
0086     union   spe_reg ts_ctsr1;               /* 0x0800 */
0087     u64 ts_ctsr2;                   /* 0x0808 */
0088     union   spe_reg ts_mtsr1;               /* 0x0810 */
0089     u64 ts_mtsr2;                   /* 0x0818 */
0090     union   spe_reg ts_itr1;                /* 0x0820 */
0091     u64 ts_itr2;                    /* 0x0828 */
0092     u64 ts_gitr;                    /* 0x0830 */
0093     u64 ts_isr;                     /* 0x0838 */
0094     u64 ts_imr;                     /* 0x0840 */
0095     union   spe_reg tm_cr1;                 /* 0x0848 */
0096     u64 tm_cr2;                     /* 0x0850 */
0097     u64 tm_simr;                    /* 0x0858 */
0098     union   ppe_spe_reg tm_tpr;             /* 0x0860 */
0099     union   spe_reg tm_str1;                /* 0x0868 */
0100     u64 tm_str2;                    /* 0x0870 */
0101     union   ppe_spe_reg tm_tsr;             /* 0x0878 */
0102
0103     /* Power Management */
0104     u64 pmcr;                       /* 0x0880 */
0105 #define CBE_PMD_PAUSE_ZERO_CONTROL  0x10000
0106     u64 pmsr;                       /* 0x0888 */
0107
0108     /* Time Base Register */
0109     u64 tbr;                        /* 0x0890 */
0110
0111     u8  pad_0x0898_0x0c00 [0x0c00 - 0x0898];        /* 0x0898 */
0112
0113     /* Fault Isolation Registers */
0114     u64 checkstop_fir;                  /* 0x0c00 */
0115     u64 recoverable_fir;                /* 0x0c08 */
0116     u64 spec_att_mchk_fir;              /* 0x0c10 */
0117     u32 fir_mode_reg;                   /* 0x0c18 */
0118     u8  pad_0x0c1c_0x0c20 [4];              /* 0x0c1c */
0119 #define CBE_PMD_FIR_MODE_M8     0x00800
0120     u64 fir_enable_mask;                /* 0x0c20 */
0121
0122     u8  pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28];        /* 0x0c28 */
0123     u64 ras_esc_0;                  /* 0x0ca8 */
0124     u8  pad_0x0cb0_0x1000 [0x1000 - 0x0cb0];        /* 0x0cb0 */
0125 };
0126
0127 extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
0128 extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
0129
0130 /*
0131  * PMU shadow registers
0132  *
0133  * Many of the registers in the performance monitoring unit are write-only,
0134  * so we need to save a copy of what we write to those registers.
0135  *
0136  * The actual data counters are read/write. However, writing to the counters
0137  * only takes effect if the PMU is enabled. Otherwise the value is stored in
0138  * a hardware latch until the next time the PMU is enabled. So we save a copy
0139  * of the counter values if we need to read them back while the PMU is
0140  * disabled. The counter_value_in_latch field is a bitmap indicating which
0141  * counters currently have a value waiting to be written.
0142  */
0143
0144 struct cbe_pmd_shadow_regs {
0145     u32 group_control;
0146     u32 debug_bus_control;
0147     u32 trace_address;
0148     u32 ext_tr_timer;
0149     u32 pm_status;
0150     u32 pm_control;
0151     u32 pm_interval;
0152     u32 pm_start_stop;
0153     u32 pm07_control[NR_CTRS];
0154
0155     u32 pm_ctr[NR_PHYS_CTRS];
0156     u32 counter_value_in_latch;
0157 };
0158
0159 extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
0160 extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
0161
0162 /*
0163  *
0164  * IIC unit register definitions
0165  *
0166  */
0167
0168 struct cbe_iic_pending_bits {
0169     u32 data;
0170     u8 flags;
0171     u8 class;
0172     u8 source;
0173     u8 prio;
0174 };
0175
0176 #define CBE_IIC_IRQ_VALID   0x80
0177 #define CBE_IIC_IRQ_IPI     0x40
0178
0179 struct cbe_iic_thread_regs {
0180     struct cbe_iic_pending_bits pending;
0181     struct cbe_iic_pending_bits pending_destr;
0182     u64 generate;
0183     u64 prio;
0184 };
0185
0186 struct cbe_iic_regs {
0187     u8  pad_0x0000_0x0400[0x0400 - 0x0000];     /* 0x0000 */
0188
0189     /* IIC interrupt registers */
0190     struct  cbe_iic_thread_regs thread[2];          /* 0x0400 */
0191
0192     u64 iic_ir;                     /* 0x0440 */
0193 #define CBE_IIC_IR_PRIO(x)      (((x) & 0xf) << 12)
0194 #define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
0195 #define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
0196 #define CBE_IIC_IR_IOC_0        0x0
0197 #define CBE_IIC_IR_IOC_1S       0xb
0198 #define CBE_IIC_IR_PT_0         0xe
0199 #define CBE_IIC_IR_PT_1         0xf
0200
0201     u64 iic_is;                     /* 0x0448 */
0202 #define CBE_IIC_IS_PMI      0x2
0203
0204     u8  pad_0x0450_0x0500[0x0500 - 0x0450];     /* 0x0450 */
0205
0206     /* IOC FIR */
0207     u64 ioc_fir_reset;                  /* 0x0500 */
0208     u64 ioc_fir_set;                    /* 0x0508 */
0209     u64 ioc_checkstop_enable;               /* 0x0510 */
0210     u64 ioc_fir_error_mask;             /* 0x0518 */
0211     u64 ioc_syserr_enable;              /* 0x0520 */
0212     u64 ioc_fir;                    /* 0x0528 */
0213
0214     u8  pad_0x0530_0x1000[0x1000 - 0x0530];     /* 0x0530 */
0215 };
0216
0217 extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
0218 extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
0219
0220
0221 struct cbe_mic_tm_regs {
0222     u8  pad_0x0000_0x0040[0x0040 - 0x0000];     /* 0x0000 */
0223
0224     u64 mic_ctl_cnfg2;                  /* 0x0040 */
0225 #define CBE_MIC_ENABLE_AUX_TRC      0x8000000000000000LL
0226 #define CBE_MIC_DISABLE_PWR_SAV_2   0x0200000000000000LL
0227 #define CBE_MIC_DISABLE_AUX_TRC_WRAP    0x0100000000000000LL
0228 #define CBE_MIC_ENABLE_AUX_TRC_INT  0x0080000000000000LL
0229
0230     u64 pad_0x0048;                 /* 0x0048 */
0231
0232     u64 mic_aux_trc_base;               /* 0x0050 */
0233     u64 mic_aux_trc_max_addr;               /* 0x0058 */
0234     u64 mic_aux_trc_cur_addr;               /* 0x0060 */
0235     u64 mic_aux_trc_grf_addr;               /* 0x0068 */
0236     u64 mic_aux_trc_grf_data;               /* 0x0070 */
0237
0238     u64 pad_0x0078;                 /* 0x0078 */
0239
0240     u64 mic_ctl_cnfg_0;                 /* 0x0080 */
0241 #define CBE_MIC_DISABLE_PWR_SAV_0   0x8000000000000000LL
0242
0243     u64 pad_0x0088;                 /* 0x0088 */
0244
0245     u64 slow_fast_timer_0;              /* 0x0090 */
0246     u64 slow_next_timer_0;              /* 0x0098 */
0247
0248     u8  pad_0x00a0_0x00f8[0x00f8 - 0x00a0];     /* 0x00a0 */
0249     u64     mic_df_ecc_address_0;               /* 0x00f8 */
0250
0251     u8  pad_0x0100_0x01b8[0x01b8 - 0x0100];     /* 0x0100 */
0252     u64     mic_df_ecc_address_1;               /* 0x01b8 */
0253
0254     u64 mic_ctl_cnfg_1;                 /* 0x01c0 */
0255 #define CBE_MIC_DISABLE_PWR_SAV_1   0x8000000000000000LL
0256
0257     u64 pad_0x01c8;                 /* 0x01c8 */
0258
0259     u64 slow_fast_timer_1;              /* 0x01d0 */
0260     u64 slow_next_timer_1;              /* 0x01d8 */
0261
0262     u8  pad_0x01e0_0x0208[0x0208 - 0x01e0];     /* 0x01e0 */
0263     u64 mic_exc;                    /* 0x0208 */
0264 #define CBE_MIC_EXC_BLOCK_SCRUB     0x0800000000000000ULL
0265 #define CBE_MIC_EXC_FAST_SCRUB      0x0100000000000000ULL
0266
0267     u64 mic_mnt_cfg;                    /* 0x0210 */
0268 #define CBE_MIC_MNT_CFG_CHAN_0_POP  0x0002000000000000ULL
0269 #define CBE_MIC_MNT_CFG_CHAN_1_POP  0x0004000000000000ULL
0270
0271     u64 mic_df_config;                  /* 0x0218 */
0272 #define CBE_MIC_ECC_DISABLE_0       0x4000000000000000ULL
0273 #define CBE_MIC_ECC_REP_SINGLE_0    0x2000000000000000ULL
0274 #define CBE_MIC_ECC_DISABLE_1       0x0080000000000000ULL
0275 #define CBE_MIC_ECC_REP_SINGLE_1    0x0040000000000000ULL
0276
0277     u8  pad_0x0220_0x0230[0x0230 - 0x0220];     /* 0x0220 */
0278     u64 mic_fir;                    /* 0x0230 */
0279 #define CBE_MIC_FIR_ECC_SINGLE_0_ERR    0x0200000000000000ULL
0280 #define CBE_MIC_FIR_ECC_MULTI_0_ERR 0x0100000000000000ULL
0281 #define CBE_MIC_FIR_ECC_SINGLE_1_ERR    0x0080000000000000ULL
0282 #define CBE_MIC_FIR_ECC_MULTI_1_ERR 0x0040000000000000ULL
0283 #define CBE_MIC_FIR_ECC_ERR_MASK    0xffff000000000000ULL
0284 #define CBE_MIC_FIR_ECC_SINGLE_0_CTE    0x0000020000000000ULL
0285 #define CBE_MIC_FIR_ECC_MULTI_0_CTE 0x0000010000000000ULL
0286 #define CBE_MIC_FIR_ECC_SINGLE_1_CTE    0x0000008000000000ULL
0287 #define CBE_MIC_FIR_ECC_MULTI_1_CTE 0x0000004000000000ULL
0288 #define CBE_MIC_FIR_ECC_CTE_MASK    0x0000ffff00000000ULL
0289 #define CBE_MIC_FIR_ECC_SINGLE_0_RESET  0x0000000002000000ULL
0290 #define CBE_MIC_FIR_ECC_MULTI_0_RESET   0x0000000001000000ULL
0291 #define CBE_MIC_FIR_ECC_SINGLE_1_RESET  0x0000000000800000ULL
0292 #define CBE_MIC_FIR_ECC_MULTI_1_RESET   0x0000000000400000ULL
0293 #define CBE_MIC_FIR_ECC_RESET_MASK  0x00000000ffff0000ULL
0294 #define CBE_MIC_FIR_ECC_SINGLE_0_SET    0x0000000000000200ULL
0295 #define CBE_MIC_FIR_ECC_MULTI_0_SET 0x0000000000000100ULL
0296 #define CBE_MIC_FIR_ECC_SINGLE_1_SET    0x0000000000000080ULL
0297 #define CBE_MIC_FIR_ECC_MULTI_1_SET 0x0000000000000040ULL
0298 #define CBE_MIC_FIR_ECC_SET_MASK    0x000000000000ffffULL
0299     u64 mic_fir_debug;                  /* 0x0238 */
0300
0301     u8  pad_0x0240_0x1000[0x1000 - 0x0240];     /* 0x0240 */
0302 };
0303
0304 extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
0305 extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
0306
0307
0308 /* Cell page table entries */
0309 #define CBE_IOPTE_PP_W      0x8000000000000000ul /* protection: write */
0310 #define CBE_IOPTE_PP_R      0x4000000000000000ul /* protection: read */
0311 #define CBE_IOPTE_M     0x2000000000000000ul /* coherency required */
0312 #define CBE_IOPTE_SO_R      0x1000000000000000ul /* ordering: writes */
0313 #define CBE_IOPTE_SO_RW     0x1800000000000000ul /* ordering: r & w */
0314 #define CBE_IOPTE_RPN_Mask  0x07fffffffffff000ul /* RPN */
0315 #define CBE_IOPTE_H     0x0000000000000800ul /* cache hint */
0316 #define CBE_IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
0317
0318 /* some utility functions to deal with SMT */
0319 extern u32 cbe_get_hw_thread_id(int cpu);
0320 extern u32 cbe_cpu_to_node(int cpu);
0321 extern u32 cbe_node_to_cpu(int node);
0322
0323 /* Init this module early */
0324 extern void cbe_regs_init(void);
0325
0326
0327 #endif /* CBE_REGS_H */