include/asm/cell-pmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Cell Broadband Engine Performance Monitor
0004  *
0005  * (C) Copyright IBM Corporation 2006
0006  *
0007  * Author:
0008  *   David Erb (djerb@us.ibm.com)
0009  *   Kevin Corry (kevcorry@us.ibm.com)
0010  */
0011
0012 #ifndef __ASM_CELL_PMU_H__
0013 #define __ASM_CELL_PMU_H__
0014
0015 /* The Cell PMU has four hardware performance counters, which can be
0016  * configured as four 32-bit counters or eight 16-bit counters.
0017  */
0018 #define NR_PHYS_CTRS 4
0019 #define NR_CTRS      (NR_PHYS_CTRS * 2)
0020
0021 /* Macros for the pm_control register. */
0022 #define CBE_PM_16BIT_CTR(ctr)              (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
0023 #define CBE_PM_ENABLE_PERF_MON             0x80000000
0024 #define CBE_PM_STOP_AT_MAX                 0x40000000
0025 #define CBE_PM_TRACE_MODE_GET(pm_control)  (((pm_control) >> 28) & 0x3)
0026 #define CBE_PM_TRACE_MODE_SET(mode)        (((mode)  & 0x3) << 28)
0027 #define CBE_PM_TRACE_BUF_OVFLW(bit)        (((bit) & 0x1) << 17)
0028 #define CBE_PM_COUNT_MODE_SET(count)       (((count) & 0x3) << 18)
0029 #define CBE_PM_FREEZE_ALL_CTRS             0x00100000
0030 #define CBE_PM_ENABLE_EXT_TRACE            0x00008000
0031 #define CBE_PM_SPU_ADDR_TRACE_SET(msk)     (((msk) & 0x3) << 9)
0032
0033 /* Macros for the trace_address register. */
0034 #define CBE_PM_TRACE_BUF_FULL              0x00000800
0035 #define CBE_PM_TRACE_BUF_EMPTY             0x00000400
0036 #define CBE_PM_TRACE_BUF_DATA_COUNT(ta)    ((ta) & 0x3ff)
0037 #define CBE_PM_TRACE_BUF_MAX_COUNT         0x400
0038
0039 /* Macros for the pm07_control registers. */
0040 #define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
0041 #define CBE_PM_CTR_INPUT_CONTROL           0x02000000
0042 #define CBE_PM_CTR_POLARITY                0x01000000
0043 #define CBE_PM_CTR_COUNT_CYCLES            0x00800000
0044 #define CBE_PM_CTR_ENABLE                  0x00400000
0045 #define PM07_CTR_INPUT_MUX(x)              (((x) & 0x3F) << 26)
0046 #define PM07_CTR_INPUT_CONTROL(x)          (((x) & 1) << 25)
0047 #define PM07_CTR_POLARITY(x)               (((x) & 1) << 24)
0048 #define PM07_CTR_COUNT_CYCLES(x)           (((x) & 1) << 23)
0049 #define PM07_CTR_ENABLE(x)                 (((x) & 1) << 22)
0050
0051 /* Macros for the pm_status register. */
0052 #define CBE_PM_CTR_OVERFLOW_INTR(ctr)      (1 << (31 - ((ctr) & 7)))
0053
0054 enum pm_reg_name {
0055     group_control,
0056     debug_bus_control,
0057     trace_address,
0058     ext_tr_timer,
0059     pm_status,
0060     pm_control,
0061     pm_interval,
0062     pm_start_stop,
0063 };
0064
0065 /* Routines for reading/writing the PMU registers. */
0066 extern u32  cbe_read_phys_ctr(u32 cpu, u32 phys_ctr);
0067 extern void cbe_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val);
0068 extern u32  cbe_read_ctr(u32 cpu, u32 ctr);
0069 extern void cbe_write_ctr(u32 cpu, u32 ctr, u32 val);
0070
0071 extern u32  cbe_read_pm07_control(u32 cpu, u32 ctr);
0072 extern void cbe_write_pm07_control(u32 cpu, u32 ctr, u32 val);
0073 extern u32  cbe_read_pm(u32 cpu, enum pm_reg_name reg);
0074 extern void cbe_write_pm(u32 cpu, enum pm_reg_name reg, u32 val);
0075
0076 extern u32  cbe_get_ctr_size(u32 cpu, u32 phys_ctr);
0077 extern void cbe_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size);
0078
0079 extern void cbe_enable_pm(u32 cpu);
0080 extern void cbe_disable_pm(u32 cpu);
0081
0082 extern void cbe_read_trace_buffer(u32 cpu, u64 *buf);
0083
0084 extern void cbe_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask);
0085 extern void cbe_disable_pm_interrupts(u32 cpu);
0086 extern u32  cbe_get_and_clear_pm_interrupts(u32 cpu);
0087 extern void cbe_sync_irq(int node);
0088
0089 #define CBE_COUNT_SUPERVISOR_MODE       0
0090 #define CBE_COUNT_HYPERVISOR_MODE       1
0091 #define CBE_COUNT_PROBLEM_MODE          2
0092 #define CBE_COUNT_ALL_MODES             3
0093
0094 #endif /* __ASM_CELL_PMU_H__ */