book3s/64/hash-64k.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H
0003 #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
0004
0005 #define H_PTE_INDEX_SIZE   8  // size: 8B <<  8 = 2KB, maps 2^8  x 64KB = 16MB
0006 #define H_PMD_INDEX_SIZE  10  // size: 8B << 10 = 8KB, maps 2^10 x 16MB = 16GB
0007 #define H_PUD_INDEX_SIZE  10  // size: 8B << 10 = 8KB, maps 2^10 x 16GB = 16TB
0008 #define H_PGD_INDEX_SIZE   8  // size: 8B <<  8 = 2KB, maps 2^8  x 16TB =  4PB
0009
0010 /*
0011  * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
0012  * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
0013  * page_to_nid does a page->section->node lookup
0014  * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
0015  * memory requirements with large number of sections.
0016  * 51 bits is the max physical real address on POWER9
0017  */
0018 #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME)
0019 #define H_MAX_PHYSMEM_BITS  51
0020 #else
0021 #define H_MAX_PHYSMEM_BITS  46
0022 #endif
0023
0024 /*
0025  * Each context is 512TB size. SLB miss for first context/default context
0026  * is handled in the hotpath.
0027  */
0028 #define MAX_EA_BITS_PER_CONTEXT     49
0029 #define REGION_SHIFT        MAX_EA_BITS_PER_CONTEXT
0030
0031 /*
0032  * We use one context for each MAP area.
0033  */
0034 #define H_KERN_MAP_SIZE     (1UL << MAX_EA_BITS_PER_CONTEXT)
0035
0036 /*
0037  * Define the address range of the kernel non-linear virtual area
0038  * 2PB
0039  */
0040 #define H_KERN_VIRT_START   ASM_CONST(0xc008000000000000)
0041
0042 /*
0043  * 64k aligned address free up few of the lower bits of RPN for us
0044  * We steal that here. For more deatils look at pte_pfn/pfn_pte()
0045  */
0046 #define H_PAGE_COMBO    _RPAGE_RPN0 /* this is a combo 4k page */
0047 #define H_PAGE_4K_PFN   _RPAGE_RPN1 /* PFN is for a single 4k page */
0048 #define H_PAGE_BUSY _RPAGE_RSV1     /* software: PTE & hash are busy */
0049 #define H_PAGE_HASHPTE  _RPAGE_RPN43    /* PTE has associated HPTE */
0050
0051 /* memory key bits. */
0052 #define H_PTE_PKEY_BIT4     _RPAGE_PKEY_BIT4
0053 #define H_PTE_PKEY_BIT3     _RPAGE_PKEY_BIT3
0054 #define H_PTE_PKEY_BIT2     _RPAGE_PKEY_BIT2
0055 #define H_PTE_PKEY_BIT1     _RPAGE_PKEY_BIT1
0056 #define H_PTE_PKEY_BIT0     _RPAGE_PKEY_BIT0
0057
0058 /*
0059  * We need to differentiate between explicit huge page and THP huge
0060  * page, since THP huge page also need to track real subpage details
0061  */
0062 #define H_PAGE_THP_HUGE  H_PAGE_4K_PFN
0063
0064 /* PTE flags to conserve for HPTE identification */
0065 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO)
0066 /*
0067  * We use a 2K PTE page fragment and another 2K for storing
0068  * real_pte_t hash index
0069  * 8 bytes per each pte entry and another 8 bytes for storing
0070  * slot details.
0071  */
0072 #define H_PTE_FRAG_SIZE_SHIFT  (H_PTE_INDEX_SIZE + 3 + 1)
0073 #define H_PTE_FRAG_NR   (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
0074
0075 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
0076 #define H_PMD_FRAG_SIZE_SHIFT  (H_PMD_INDEX_SIZE + 3 + 1)
0077 #else
0078 #define H_PMD_FRAG_SIZE_SHIFT  (H_PMD_INDEX_SIZE + 3)
0079 #endif
0080 #define H_PMD_FRAG_NR   (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
0081
0082 #ifndef __ASSEMBLY__
0083 #include <asm/errno.h>
0084
0085 /*
0086  * With 64K pages on hash table, we have a special PTE format that
0087  * uses a second "half" of the page table to encode sub-page information
0088  * in order to deal with 64K made of 4K HW pages. Thus we override the
0089  * generic accessors and iterators here
0090  */
0091 #define __real_pte __real_pte
0092 static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
0093 {
0094     real_pte_t rpte;
0095     unsigned long *hidxp;
0096
0097     rpte.pte = pte;
0098
0099     /*
0100      * Ensure that we do not read the hidx before we read the PTE. Because
0101      * the writer side is expected to finish writing the hidx first followed
0102      * by the PTE, by using smp_wmb(). pte_set_hash_slot() ensures that.
0103      */
0104     smp_rmb();
0105
0106     hidxp = (unsigned long *)(ptep + offset);
0107     rpte.hidx = *hidxp;
0108     return rpte;
0109 }
0110
0111 /*
0112  * shift the hidx representation by one-modulo-0xf; i.e hidx 0 is respresented
0113  * as 1, 1 as 2,... , and 0xf as 0.  This convention lets us represent a
0114  * invalid hidx 0xf with a 0x0 bit value. PTEs are anyway zero'd when
0115  * allocated. We dont have to zero them gain; thus save on the initialization.
0116  */
0117 #define HIDX_UNSHIFT_BY_ONE(x) ((x + 0xfUL) & 0xfUL) /* shift backward by one */
0118 #define HIDX_SHIFT_BY_ONE(x) ((x + 0x1UL) & 0xfUL)   /* shift forward by one */
0119 #define HIDX_BITS(x, index)  (x << (index << 2))
0120 #define BITS_TO_HIDX(x, index)  ((x >> (index << 2)) & 0xfUL)
0121 #define INVALID_RPTE_HIDX  0x0UL
0122
0123 static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
0124 {
0125     return HIDX_UNSHIFT_BY_ONE(BITS_TO_HIDX(rpte.hidx, index));
0126 }
0127
0128 /*
0129  * Commit the hidx and return PTE bits that needs to be modified. The caller is
0130  * expected to modify the PTE bits accordingly and commit the PTE to memory.
0131  */
0132 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
0133                      unsigned int subpg_index,
0134                      unsigned long hidx, int offset)
0135 {
0136     unsigned long *hidxp = (unsigned long *)(ptep + offset);
0137
0138     rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index);
0139     *hidxp = rpte.hidx  | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index);
0140
0141     /*
0142      * Anyone reading PTE must ensure hidx bits are read after reading the
0143      * PTE by using the read-side barrier smp_rmb(). __real_pte() can be
0144      * used for that.
0145      */
0146     smp_wmb();
0147
0148     /* No PTE bits to be modified, return 0x0UL */
0149     return 0x0UL;
0150 }
0151
0152 #define __rpte_to_pte(r)    ((r).pte)
0153 extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);
0154 /*
0155  * Trick: we set __end to va + 64k, which happens works for
0156  * a 16M page as well as we want only one iteration
0157  */
0158 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
0159     do {                                \
0160         unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT));  \
0161         unsigned __split = (psize == MMU_PAGE_4K ||     \
0162                     psize == MMU_PAGE_64K_AP);      \
0163         shift = mmu_psize_defs[psize].shift;            \
0164         for (index = 0; vpn < __end; index++,           \
0165                  vpn += (1L << (shift - VPN_SHIFT))) {  \
0166         if (!__split || __rpte_sub_valid(rpte, index))
0167
0168 #define pte_iterate_hashed_end()  } } while(0)
0169
0170 #define pte_pagesize_index(mm, addr, pte)   \
0171     (((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
0172
0173 extern int remap_pfn_range(struct vm_area_struct *, unsigned long addr,
0174                unsigned long pfn, unsigned long size, pgprot_t);
0175 static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long addr,
0176                  unsigned long pfn, pgprot_t prot)
0177 {
0178     if (pfn > (PTE_RPN_MASK >> PAGE_SHIFT)) {
0179         WARN(1, "remap_4k_pfn called with wrong pfn value\n");
0180         return -EINVAL;
0181     }
0182     return remap_pfn_range(vma, addr, pfn, PAGE_SIZE,
0183                    __pgprot(pgprot_val(prot) | H_PAGE_4K_PFN));
0184 }
0185
0186 #define H_PTE_TABLE_SIZE    PTE_FRAG_SIZE
0187 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE)
0188 #define H_PMD_TABLE_SIZE    ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \
0189                  (sizeof(unsigned long) << PMD_INDEX_SIZE))
0190 #else
0191 #define H_PMD_TABLE_SIZE    (sizeof(pmd_t) << PMD_INDEX_SIZE)
0192 #endif
0193 #ifdef CONFIG_HUGETLB_PAGE
0194 #define H_PUD_TABLE_SIZE    ((sizeof(pud_t) << PUD_INDEX_SIZE) +    \
0195                  (sizeof(unsigned long) << PUD_INDEX_SIZE))
0196 #else
0197 #define H_PUD_TABLE_SIZE    (sizeof(pud_t) << PUD_INDEX_SIZE)
0198 #endif
0199 #define H_PGD_TABLE_SIZE    (sizeof(pgd_t) << PGD_INDEX_SIZE)
0200
0201 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
0202 static inline char *get_hpte_slot_array(pmd_t *pmdp)
0203 {
0204     /*
0205      * The hpte hindex is stored in the pgtable whose address is in the
0206      * second half of the PMD
0207      *
0208      * Order this load with the test for pmd_trans_huge in the caller
0209      */
0210     smp_rmb();
0211     return *(char **)(pmdp + PTRS_PER_PMD);
0212
0213
0214 }
0215 /*
0216  * The linux hugepage PMD now include the pmd entries followed by the address
0217  * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
0218  * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per
0219  * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
0220  * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
0221  *
0222  * The top three bits are intentionally left as zero. This memory location
0223  * are also used as normal page PTE pointers. So if we have any pointers
0224  * left around while we collapse a hugepage, we need to make sure
0225  * _PAGE_PRESENT bit of that is zero when we look at them
0226  */
0227 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
0228 {
0229     return hpte_slot_array[index] & 0x1;
0230 }
0231
0232 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
0233                        int index)
0234 {
0235     return hpte_slot_array[index] >> 1;
0236 }
0237
0238 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
0239                     unsigned int index, unsigned int hidx)
0240 {
0241     hpte_slot_array[index] = (hidx << 1) | 0x1;
0242 }
0243
0244 /*
0245  *
0246  * For core kernel code by design pmd_trans_huge is never run on any hugetlbfs
0247  * page. The hugetlbfs page table walking and mangling paths are totally
0248  * separated form the core VM paths and they're differentiated by
0249  *  VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run.
0250  *
0251  * pmd_trans_huge() is defined as false at build time if
0252  * CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build
0253  * time in such case.
0254  *
0255  * For ppc64 we need to differntiate from explicit hugepages from THP, because
0256  * for THP we also track the subpage details at the pmd level. We don't do
0257  * that for explicit huge pages.
0258  *
0259  */
0260 static inline int hash__pmd_trans_huge(pmd_t pmd)
0261 {
0262     return !!((pmd_val(pmd) & (_PAGE_PTE | H_PAGE_THP_HUGE | _PAGE_DEVMAP)) ==
0263           (_PAGE_PTE | H_PAGE_THP_HUGE));
0264 }
0265
0266 static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
0267 {
0268     return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
0269 }
0270
0271 static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
0272 {
0273     return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
0274 }
0275
0276 extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
0277                        unsigned long addr, pmd_t *pmdp,
0278                        unsigned long clr, unsigned long set);
0279 extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
0280                    unsigned long address, pmd_t *pmdp);
0281 extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
0282                      pgtable_t pgtable);
0283 extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
0284 extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
0285                        unsigned long addr, pmd_t *pmdp);
0286 extern int hash__has_transparent_hugepage(void);
0287 #endif /*  CONFIG_TRANSPARENT_HUGEPAGE */
0288
0289 static inline pmd_t hash__pmd_mkdevmap(pmd_t pmd)
0290 {
0291     return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE | _PAGE_DEVMAP));
0292 }
0293
0294 #endif  /* __ASSEMBLY__ */
0295
0296 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */