include/asm/barrier.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
0004  */
0005 #ifndef _ASM_POWERPC_BARRIER_H
0006 #define _ASM_POWERPC_BARRIER_H
0007
0008 #include <asm/asm-const.h>
0009
0010 #ifndef __ASSEMBLY__
0011 #include <asm/ppc-opcode.h>
0012 #endif
0013
0014 /*
0015  * Memory barrier.
0016  * The sync instruction guarantees that all memory accesses initiated
0017  * by this processor have been performed (with respect to all other
0018  * mechanisms that access memory).  The eieio instruction is a barrier
0019  * providing an ordering (separately) for (a) cacheable stores and (b)
0020  * loads and stores to non-cacheable memory (e.g. I/O devices).
0021  *
0022  * mb() prevents loads and stores being reordered across this point.
0023  * rmb() prevents loads being reordered across this point.
0024  * wmb() prevents stores being reordered across this point.
0025  *
0026  * *mb() variants without smp_ prefix must order all types of memory
0027  * operations with one another. sync is the only instruction sufficient
0028  * to do this.
0029  *
0030  * For the smp_ barriers, ordering is for cacheable memory operations
0031  * only. We have to use the sync instruction for smp_mb(), since lwsync
0032  * doesn't order loads with respect to previous stores.  Lwsync can be
0033  * used for smp_rmb() and smp_wmb().
0034  *
0035  * However, on CPUs that don't support lwsync, lwsync actually maps to a
0036  * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
0037  */
0038 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
0039 #define rmb()  __asm__ __volatile__ ("sync" : : : "memory")
0040 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
0041
0042 /* The sub-arch has lwsync */
0043 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_E500MC)
0044 #    define SMPWMB      LWSYNC
0045 #elif defined(CONFIG_BOOKE)
0046 #    define SMPWMB      mbar
0047 #else
0048 #    define SMPWMB      eieio
0049 #endif
0050
0051 /* clang defines this macro for a builtin, which will not work with runtime patching */
0052 #undef __lwsync
0053 #define __lwsync()  __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
0054 #define dma_rmb()   __lwsync()
0055 #define dma_wmb()   __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
0056
0057 #define __smp_lwsync()  __lwsync()
0058
0059 #define __smp_mb()  mb()
0060 #define __smp_rmb() __lwsync()
0061 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
0062
0063 /*
0064  * This is a barrier which prevents following instructions from being
0065  * started until the value of the argument x is known.  For example, if
0066  * x is a variable loaded from memory, this prevents following
0067  * instructions from being executed until the load has been performed.
0068  */
0069 #define data_barrier(x) \
0070     asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
0071
0072 #define __smp_store_release(p, v)                       \
0073 do {                                    \
0074     compiletime_assert_atomic_type(*p);             \
0075     __smp_lwsync();                         \
0076     WRITE_ONCE(*p, v);                      \
0077 } while (0)
0078
0079 #define __smp_load_acquire(p)                       \
0080 ({                                  \
0081     typeof(*p) ___p1 = READ_ONCE(*p);               \
0082     compiletime_assert_atomic_type(*p);             \
0083     __smp_lwsync();                         \
0084     ___p1;                              \
0085 })
0086
0087 #ifdef CONFIG_PPC_BOOK3S_64
0088 #define NOSPEC_BARRIER_SLOT   nop
0089 #elif defined(CONFIG_PPC_FSL_BOOK3E)
0090 #define NOSPEC_BARRIER_SLOT   nop; nop
0091 #endif
0092
0093 #ifdef CONFIG_PPC_BARRIER_NOSPEC
0094 /*
0095  * Prevent execution of subsequent instructions until preceding branches have
0096  * been fully resolved and are no longer executing speculatively.
0097  */
0098 #define barrier_nospec_asm NOSPEC_BARRIER_FIXUP_SECTION; NOSPEC_BARRIER_SLOT
0099
0100 // This also acts as a compiler barrier due to the memory clobber.
0101 #define barrier_nospec() asm (stringify_in_c(barrier_nospec_asm) ::: "memory")
0102
0103 #else /* !CONFIG_PPC_BARRIER_NOSPEC */
0104 #define barrier_nospec_asm
0105 #define barrier_nospec()
0106 #endif /* CONFIG_PPC_BARRIER_NOSPEC */
0107
0108 /*
0109  * pmem_wmb() ensures that all stores for which the modification
0110  * are written to persistent storage by preceding dcbfps/dcbstps
0111  * instructions have updated persistent storage before any data
0112  * access or data transfer caused by subsequent instructions is
0113  * initiated.
0114  */
0115 #define pmem_wmb() __asm__ __volatile__(PPC_PHWSYNC ::: "memory")
0116
0117 #include <asm-generic/barrier.h>
0118
0119 #endif /* _ASM_POWERPC_BARRIER_H */