include/asm/8xx_immap.h

0001 /*
0002  * MPC8xx Internal Memory Map
0003  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
0004  *
0005  * The I/O on the MPC860 is comprised of blocks of special registers
0006  * and the dual port ram for the Communication Processor Module.
0007  * Within this space are functional units such as the SIU, memory
0008  * controller, system timers, and other control functions.  It is
0009  * a combination that I found difficult to separate into logical
0010  * functional files.....but anyone else is welcome to try.  -- Dan
0011  */
0012 #ifdef __KERNEL__
0013 #ifndef __IMMAP_8XX__
0014 #define __IMMAP_8XX__
0015
0016 /* System configuration registers.
0017 */
0018 typedef struct sys_conf {
0019     uint    sc_siumcr;
0020     uint    sc_sypcr;
0021     uint    sc_swt;
0022     char    res1[2];
0023     ushort  sc_swsr;
0024     uint    sc_sipend;
0025     uint    sc_simask;
0026     uint    sc_siel;
0027     uint    sc_sivec;
0028     uint    sc_tesr;
0029     char    res2[0xc];
0030     uint    sc_sdcr;
0031     char    res3[0x4c];
0032 } sysconf8xx_t;
0033
0034 /* PCMCIA configuration registers.
0035 */
0036 typedef struct pcmcia_conf {
0037     uint    pcmc_pbr0;
0038     uint    pcmc_por0;
0039     uint    pcmc_pbr1;
0040     uint    pcmc_por1;
0041     uint    pcmc_pbr2;
0042     uint    pcmc_por2;
0043     uint    pcmc_pbr3;
0044     uint    pcmc_por3;
0045     uint    pcmc_pbr4;
0046     uint    pcmc_por4;
0047     uint    pcmc_pbr5;
0048     uint    pcmc_por5;
0049     uint    pcmc_pbr6;
0050     uint    pcmc_por6;
0051     uint    pcmc_pbr7;
0052     uint    pcmc_por7;
0053     char    res1[0x20];
0054     uint    pcmc_pgcra;
0055     uint    pcmc_pgcrb;
0056     uint    pcmc_pscr;
0057     char    res2[4];
0058     uint    pcmc_pipr;
0059     char    res3[4];
0060     uint    pcmc_per;
0061     char    res4[4];
0062 } pcmconf8xx_t;
0063
0064 /* Memory controller registers.
0065 */
0066 typedef struct  mem_ctlr {
0067     uint    memc_br0;
0068     uint    memc_or0;
0069     uint    memc_br1;
0070     uint    memc_or1;
0071     uint    memc_br2;
0072     uint    memc_or2;
0073     uint    memc_br3;
0074     uint    memc_or3;
0075     uint    memc_br4;
0076     uint    memc_or4;
0077     uint    memc_br5;
0078     uint    memc_or5;
0079     uint    memc_br6;
0080     uint    memc_or6;
0081     uint    memc_br7;
0082     uint    memc_or7;
0083     char    res1[0x24];
0084     uint    memc_mar;
0085     uint    memc_mcr;
0086     char    res2[4];
0087     uint    memc_mamr;
0088     uint    memc_mbmr;
0089     ushort  memc_mstat;
0090     ushort  memc_mptpr;
0091     uint    memc_mdr;
0092     char    res3[0x80];
0093 } memctl8xx_t;
0094
0095 /*-----------------------------------------------------------------------
0096  * BR - Memory Controller: Base Register                    16-9
0097  */
0098 #define BR_BA_MSK   0xffff8000  /* Base Address Mask            */
0099 #define BR_AT_MSK   0x00007000  /* Address Type Mask            */
0100 #define BR_PS_MSK   0x00000c00  /* Port Size Mask           */
0101 #define BR_PS_32    0x00000000  /* 32 bit port size         */
0102 #define BR_PS_16    0x00000800  /* 16 bit port size         */
0103 #define BR_PS_8     0x00000400  /*  8 bit port size         */
0104 #define BR_PARE     0x00000200  /* Parity Enable            */
0105 #define BR_WP       0x00000100  /* Write Protect            */
0106 #define BR_MS_MSK   0x000000c0  /* Machine Select Mask          */
0107 #define BR_MS_GPCM  0x00000000  /* G.P.C.M. Machine Select      */
0108 #define BR_MS_UPMA  0x00000080  /* U.P.M.A Machine Select       */
0109 #define BR_MS_UPMB  0x000000c0  /* U.P.M.B Machine Select       */
0110 #define BR_V        0x00000001  /* Bank Valid               */
0111
0112 /*-----------------------------------------------------------------------
0113  * OR - Memory Controller: Option Register              16-11
0114  */
0115 #define OR_AM_MSK   0xffff8000  /* Address Mask Mask            */
0116 #define OR_ATM_MSK  0x00007000  /* Address Type Mask Mask       */
0117 #define OR_CSNT_SAM 0x00000800  /* Chip Select Negation Time/ Start */
0118                     /* Address Multiplex            */
0119 #define OR_ACS_MSK  0x00000600  /* Address to Chip Select Setup mask    */
0120 #define OR_ACS_DIV1 0x00000000  /* CS is output at the same time    */
0121 #define OR_ACS_DIV4 0x00000400  /* CS is output 1/4 a clock later   */
0122 #define OR_ACS_DIV2 0x00000600  /* CS is output 1/2 a clock later   */
0123 #define OR_G5LA     0x00000400  /* Output #GPL5 on #GPL_A5      */
0124 #define OR_G5LS     0x00000200  /* Drive #GPL high on falling edge of...*/
0125 #define OR_BI       0x00000100  /* Burst inhibit            */
0126 #define OR_SCY_MSK  0x000000f0  /* Cycle Length in Clocks       */
0127 #define OR_SCY_0_CLK    0x00000000  /* 0 clock cycles wait states       */
0128 #define OR_SCY_1_CLK    0x00000010  /* 1 clock cycles wait states       */
0129 #define OR_SCY_2_CLK    0x00000020  /* 2 clock cycles wait states       */
0130 #define OR_SCY_3_CLK    0x00000030  /* 3 clock cycles wait states       */
0131 #define OR_SCY_4_CLK    0x00000040  /* 4 clock cycles wait states       */
0132 #define OR_SCY_5_CLK    0x00000050  /* 5 clock cycles wait states       */
0133 #define OR_SCY_6_CLK    0x00000060  /* 6 clock cycles wait states       */
0134 #define OR_SCY_7_CLK    0x00000070  /* 7 clock cycles wait states       */
0135 #define OR_SCY_8_CLK    0x00000080  /* 8 clock cycles wait states       */
0136 #define OR_SCY_9_CLK    0x00000090  /* 9 clock cycles wait states       */
0137 #define OR_SCY_10_CLK   0x000000a0  /* 10 clock cycles wait states      */
0138 #define OR_SCY_11_CLK   0x000000b0  /* 11 clock cycles wait states      */
0139 #define OR_SCY_12_CLK   0x000000c0  /* 12 clock cycles wait states      */
0140 #define OR_SCY_13_CLK   0x000000d0  /* 13 clock cycles wait states      */
0141 #define OR_SCY_14_CLK   0x000000e0  /* 14 clock cycles wait states      */
0142 #define OR_SCY_15_CLK   0x000000f0  /* 15 clock cycles wait states      */
0143 #define OR_SETA     0x00000008  /* External Transfer Acknowledge    */
0144 #define OR_TRLX     0x00000004  /* Timing Relaxed           */
0145 #define OR_EHTR     0x00000002  /* Extended Hold Time on Read       */
0146
0147 /* System Integration Timers.
0148 */
0149 typedef struct  sys_int_timers {
0150     ushort  sit_tbscr;
0151     char    res0[0x02];
0152     uint    sit_tbreff0;
0153     uint    sit_tbreff1;
0154     char    res1[0x14];
0155     ushort  sit_rtcsc;
0156     char    res2[0x02];
0157     uint    sit_rtc;
0158     uint    sit_rtsec;
0159     uint    sit_rtcal;
0160     char    res3[0x10];
0161     ushort  sit_piscr;
0162     char    res4[2];
0163     uint    sit_pitc;
0164     uint    sit_pitr;
0165     char    res5[0x34];
0166 } sit8xx_t;
0167
0168 #define TBSCR_TBIRQ_MASK    ((ushort)0xff00)
0169 #define TBSCR_REFA      ((ushort)0x0080)
0170 #define TBSCR_REFB      ((ushort)0x0040)
0171 #define TBSCR_REFAE     ((ushort)0x0008)
0172 #define TBSCR_REFBE     ((ushort)0x0004)
0173 #define TBSCR_TBF       ((ushort)0x0002)
0174 #define TBSCR_TBE       ((ushort)0x0001)
0175
0176 #define RTCSC_RTCIRQ_MASK   ((ushort)0xff00)
0177 #define RTCSC_SEC       ((ushort)0x0080)
0178 #define RTCSC_ALR       ((ushort)0x0040)
0179 #define RTCSC_38K       ((ushort)0x0010)
0180 #define RTCSC_SIE       ((ushort)0x0008)
0181 #define RTCSC_ALE       ((ushort)0x0004)
0182 #define RTCSC_RTF       ((ushort)0x0002)
0183 #define RTCSC_RTE       ((ushort)0x0001)
0184
0185 #define PISCR_PIRQ_MASK     ((ushort)0xff00)
0186 #define PISCR_PS        ((ushort)0x0080)
0187 #define PISCR_PIE       ((ushort)0x0004)
0188 #define PISCR_PTF       ((ushort)0x0002)
0189 #define PISCR_PTE       ((ushort)0x0001)
0190
0191 /* Clocks and Reset.
0192 */
0193 typedef struct clk_and_reset {
0194     uint    car_sccr;
0195     uint    car_plprcr;
0196     uint    car_rsr;
0197     char    res[0x74];        /* Reserved area                  */
0198 } car8xx_t;
0199
0200 /* System Integration Timers keys.
0201 */
0202 typedef struct sitk {
0203     uint    sitk_tbscrk;
0204     uint    sitk_tbreff0k;
0205     uint    sitk_tbreff1k;
0206     uint    sitk_tbk;
0207     char    res1[0x10];
0208     uint    sitk_rtcsck;
0209     uint    sitk_rtck;
0210     uint    sitk_rtseck;
0211     uint    sitk_rtcalk;
0212     char    res2[0x10];
0213     uint    sitk_piscrk;
0214     uint    sitk_pitck;
0215     char    res3[0x38];
0216 } sitk8xx_t;
0217
0218 /* Clocks and reset keys.
0219 */
0220 typedef struct cark {
0221     uint    cark_sccrk;
0222     uint    cark_plprcrk;
0223     uint    cark_rsrk;
0224     char    res[0x474];
0225 } cark8xx_t;
0226
0227 /* The key to unlock registers maintained by keep-alive power.
0228 */
0229 #define KAPWR_KEY   ((unsigned int)0x55ccaa33)
0230
0231 /* Video interface.  MPC823 Only.
0232 */
0233 typedef struct vid823 {
0234     ushort  vid_vccr;
0235     ushort  res1;
0236     u_char  vid_vsr;
0237     u_char  res2;
0238     u_char  vid_vcmr;
0239     u_char  res3;
0240     uint    vid_vbcb;
0241     uint    res4;
0242     uint    vid_vfcr0;
0243     uint    vid_vfaa0;
0244     uint    vid_vfba0;
0245     uint    vid_vfcr1;
0246     uint    vid_vfaa1;
0247     uint    vid_vfba1;
0248     u_char  res5[0x18];
0249 } vid823_t;
0250
0251 /* LCD interface.  823 Only.
0252 */
0253 typedef struct lcd {
0254     uint    lcd_lccr;
0255     uint    lcd_lchcr;
0256     uint    lcd_lcvcr;
0257     char    res1[4];
0258     uint    lcd_lcfaa;
0259     uint    lcd_lcfba;
0260     char    lcd_lcsr;
0261     char    res2[0x7];
0262 } lcd823_t;
0263
0264 /* I2C
0265 */
0266 typedef struct i2c {
0267     u_char  i2c_i2mod;
0268     char    res1[3];
0269     u_char  i2c_i2add;
0270     char    res2[3];
0271     u_char  i2c_i2brg;
0272     char    res3[3];
0273     u_char  i2c_i2com;
0274     char    res4[3];
0275     u_char  i2c_i2cer;
0276     char    res5[3];
0277     u_char  i2c_i2cmr;
0278     char    res6[0x8b];
0279 } i2c8xx_t;
0280
0281 /* DMA control/status registers.
0282 */
0283 typedef struct sdma_csr {
0284     char    res1[4];
0285     uint    sdma_sdar;
0286     u_char  sdma_sdsr;
0287     char    res3[3];
0288     u_char  sdma_sdmr;
0289     char    res4[3];
0290     u_char  sdma_idsr1;
0291     char    res5[3];
0292     u_char  sdma_idmr1;
0293     char    res6[3];
0294     u_char  sdma_idsr2;
0295     char    res7[3];
0296     u_char  sdma_idmr2;
0297     char    res8[0x13];
0298 } sdma8xx_t;
0299
0300 /* Communication Processor Module Interrupt Controller.
0301 */
0302 typedef struct cpm_ic {
0303     ushort  cpic_civr;
0304     char    res[0xe];
0305     uint    cpic_cicr;
0306     uint    cpic_cipr;
0307     uint    cpic_cimr;
0308     uint    cpic_cisr;
0309 } cpic8xx_t;
0310
0311 /* Input/Output Port control/status registers.
0312 */
0313 typedef struct io_port {
0314     ushort  iop_padir;
0315     ushort  iop_papar;
0316     ushort  iop_paodr;
0317     ushort  iop_padat;
0318     char    res1[8];
0319     ushort  iop_pcdir;
0320     ushort  iop_pcpar;
0321     ushort  iop_pcso;
0322     ushort  iop_pcdat;
0323     ushort  iop_pcint;
0324     char    res2[6];
0325     ushort  iop_pddir;
0326     ushort  iop_pdpar;
0327     char    res3[2];
0328     ushort  iop_pddat;
0329     uint    utmode;
0330     char    res4[4];
0331 } iop8xx_t;
0332
0333 /* Communication Processor Module Timers
0334 */
0335 typedef struct cpm_timers {
0336     ushort  cpmt_tgcr;
0337     char    res1[0xe];
0338     ushort  cpmt_tmr1;
0339     ushort  cpmt_tmr2;
0340     ushort  cpmt_trr1;
0341     ushort  cpmt_trr2;
0342     ushort  cpmt_tcr1;
0343     ushort  cpmt_tcr2;
0344     ushort  cpmt_tcn1;
0345     ushort  cpmt_tcn2;
0346     ushort  cpmt_tmr3;
0347     ushort  cpmt_tmr4;
0348     ushort  cpmt_trr3;
0349     ushort  cpmt_trr4;
0350     ushort  cpmt_tcr3;
0351     ushort  cpmt_tcr4;
0352     ushort  cpmt_tcn3;
0353     ushort  cpmt_tcn4;
0354     ushort  cpmt_ter1;
0355     ushort  cpmt_ter2;
0356     ushort  cpmt_ter3;
0357     ushort  cpmt_ter4;
0358     char    res2[8];
0359 } cpmtimer8xx_t;
0360
0361 /* Finally, the Communication Processor stuff.....
0362 */
0363 typedef struct scc {        /* Serial communication channels */
0364     uint    scc_gsmrl;
0365     uint    scc_gsmrh;
0366     ushort  scc_psmr;
0367     char    res1[2];
0368     ushort  scc_todr;
0369     ushort  scc_dsr;
0370     ushort  scc_scce;
0371     char    res2[2];
0372     ushort  scc_sccm;
0373     char    res3;
0374     u_char  scc_sccs;
0375     char    res4[8];
0376 } scc_t;
0377
0378 typedef struct smc {        /* Serial management channels */
0379     char    res1[2];
0380     ushort  smc_smcmr;
0381     char    res2[2];
0382     u_char  smc_smce;
0383     char    res3[3];
0384     u_char  smc_smcm;
0385     char    res4[5];
0386 } smc_t;
0387
0388 /* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
0389  * it fits within the address space.
0390  */
0391
0392 typedef struct fec {
0393     uint    fec_addr_low;       /* lower 32 bits of station address */
0394     ushort  fec_addr_high;      /* upper 16 bits of station address */
0395     ushort  res1;           /* reserved             */
0396     uint    fec_grp_hash_table_high;    /* upper 32-bits of hash table      */
0397     uint    fec_grp_hash_table_low; /* lower 32-bits of hash table      */
0398     uint    fec_r_des_start;    /* beginning of Rx descriptor ring  */
0399     uint    fec_x_des_start;    /* beginning of Tx descriptor ring  */
0400     uint    fec_r_buff_size;    /* Rx buffer size           */
0401     uint    res2[9];        /* reserved             */
0402     uint    fec_ecntrl;     /* ethernet control register        */
0403     uint    fec_ievent;     /* interrupt event register     */
0404     uint    fec_imask;      /* interrupt mask register      */
0405     uint    fec_ivec;       /* interrupt level and vector status    */
0406     uint    fec_r_des_active;   /* Rx ring updated flag         */
0407     uint    fec_x_des_active;   /* Tx ring updated flag         */
0408     uint    res3[10];       /* reserved             */
0409     uint    fec_mii_data;       /* MII data register            */
0410     uint    fec_mii_speed;      /* MII speed control register       */
0411     uint    res4[17];       /* reserved             */
0412     uint    fec_r_bound;        /* end of RAM (read-only)       */
0413     uint    fec_r_fstart;       /* Rx FIFO start address        */
0414     uint    res5[6];        /* reserved             */
0415     uint    fec_x_fstart;       /* Tx FIFO start address        */
0416     uint    res6[17];       /* reserved             */
0417     uint    fec_fun_code;       /* fec SDMA function code       */
0418     uint    res7[3];        /* reserved             */
0419     uint    fec_r_cntrl;        /* Rx control register          */
0420     uint    fec_r_hash;     /* Rx hash register         */
0421     uint    res8[14];       /* reserved             */
0422     uint    fec_x_cntrl;        /* Tx control register          */
0423     uint    res9[0x1e];     /* reserved             */
0424 } fec_t;
0425
0426 /* The FEC and LCD color map share the same address space....
0427  * I guess we will never see an 823T :-).
0428  */
0429 union fec_lcd {
0430     fec_t   fl_un_fec;
0431     u_char  fl_un_cmap[0x200];
0432 };
0433
0434 typedef struct comm_proc {
0435     /* General control and status registers.
0436     */
0437     ushort  cp_cpcr;
0438     u_char  res1[2];
0439     ushort  cp_rccr;
0440     u_char  res2;
0441     u_char  cp_rmds;
0442     u_char  res3[4];
0443     ushort  cp_cpmcr1;
0444     ushort  cp_cpmcr2;
0445     ushort  cp_cpmcr3;
0446     ushort  cp_cpmcr4;
0447     u_char  res4[2];
0448     ushort  cp_rter;
0449     u_char  res5[2];
0450     ushort  cp_rtmr;
0451     u_char  res6[0x14];
0452
0453     /* Baud rate generators.
0454     */
0455     uint    cp_brgc1;
0456     uint    cp_brgc2;
0457     uint    cp_brgc3;
0458     uint    cp_brgc4;
0459
0460     /* Serial Communication Channels.
0461     */
0462     scc_t   cp_scc[4];
0463
0464     /* Serial Management Channels.
0465     */
0466     smc_t   cp_smc[2];
0467
0468     /* Serial Peripheral Interface.
0469     */
0470     ushort  cp_spmode;
0471     u_char  res7[4];
0472     u_char  cp_spie;
0473     u_char  res8[3];
0474     u_char  cp_spim;
0475     u_char  res9[2];
0476     u_char  cp_spcom;
0477     u_char  res10[2];
0478
0479     /* Parallel Interface Port.
0480     */
0481     u_char  res11[2];
0482     ushort  cp_pipc;
0483     u_char  res12[2];
0484     ushort  cp_ptpr;
0485     uint    cp_pbdir;
0486     uint    cp_pbpar;
0487     u_char  res13[2];
0488     ushort  cp_pbodr;
0489     uint    cp_pbdat;
0490
0491     /* Port E - MPC87x/88x only.
0492      */
0493     uint    cp_pedir;
0494     uint    cp_pepar;
0495     uint    cp_peso;
0496     uint    cp_peodr;
0497     uint    cp_pedat;
0498
0499     /* Communications Processor Timing Register -
0500        Contains RMII Timing for the FECs on MPC87x/88x only.
0501     */
0502     uint    cp_cptr;
0503
0504     /* Serial Interface and Time Slot Assignment.
0505     */
0506     uint    cp_simode;
0507     u_char  cp_sigmr;
0508     u_char  res15;
0509     u_char  cp_sistr;
0510     u_char  cp_sicmr;
0511     u_char  res16[4];
0512     uint    cp_sicr;
0513     uint    cp_sirp;
0514     u_char  res17[0xc];
0515
0516     /* 256 bytes of MPC823 video controller RAM array.
0517     */
0518     u_char  cp_vcram[0x100];
0519     u_char  cp_siram[0x200];
0520
0521     /* The fast ethernet controller is not really part of the CPM,
0522      * but it resides in the address space.
0523      * The LCD color map is also here.
0524      */
0525     union   fec_lcd fl_un;
0526 #define cp_fec      fl_un.fl_un_fec
0527 #define lcd_cmap    fl_un.fl_un_cmap
0528     char    res18[0xE00];
0529
0530     /* The DUET family has a second FEC here */
0531     fec_t   cp_fec2;
0532 #define cp_fec1 cp_fec  /* consistency macro */
0533
0534     /* Dual Ported RAM follows.
0535      * There are many different formats for this memory area
0536      * depending upon the devices used and options chosen.
0537      * Some processors don't have all of it populated.
0538      */
0539     u_char  cp_dpmem[0x1C00];   /* BD / Data / ucode */
0540     u_char  cp_dparam[0x400];   /* Parameter RAM */
0541 } cpm8xx_t;
0542
0543 /* Internal memory map.
0544 */
0545 typedef struct immap {
0546     sysconf8xx_t    im_siu_conf;    /* SIU Configuration */
0547     pcmconf8xx_t    im_pcmcia;  /* PCMCIA Configuration */
0548     memctl8xx_t im_memctl;  /* Memory Controller */
0549     sit8xx_t    im_sit;     /* System integration timers */
0550     car8xx_t    im_clkrst;  /* Clocks and reset */
0551     sitk8xx_t   im_sitk;    /* Sys int timer keys */
0552     cark8xx_t   im_clkrstk; /* Clocks and reset keys */
0553     vid823_t    im_vid;     /* Video (823 only) */
0554     lcd823_t    im_lcd;     /* LCD (823 only) */
0555     i2c8xx_t    im_i2c;     /* I2C control/status */
0556     sdma8xx_t   im_sdma;    /* SDMA control/status */
0557     cpic8xx_t   im_cpic;    /* CPM Interrupt Controller */
0558     iop8xx_t    im_ioport;  /* IO Port control/status */
0559     cpmtimer8xx_t   im_cpmtimer;    /* CPM timers */
0560     cpm8xx_t    im_cpm;     /* Communication processor */
0561 } immap_t;
0562
0563 #endif /* __IMMAP_8XX__ */
0564 #endif /* __KERNEL__ */