OSCL-LXR |
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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Common registers for PPC AES implementation 0004 * 0005 * Copyright (c) 2015 Markus Stockhausen <stockhausen@collogia.de> 0006 */ 0007 0008 #define rKS r0 /* copy of en-/decryption key pointer */ 0009 #define rDP r3 /* destination pointer */ 0010 #define rSP r4 /* source pointer */ 0011 #define rKP r5 /* pointer to en-/decryption key pointer */ 0012 #define rRR r6 /* en-/decryption rounds */ 0013 #define rLN r7 /* length of data to be processed */ 0014 #define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */ 0015 #define rKT r9 /* pointer to tweak key (XTS mode) */ 0016 #define rT0 r11 /* pointers to en-/decryption tables */ 0017 #define rT1 r10 0018 #define rD0 r9 /* data */ 0019 #define rD1 r14 0020 #define rD2 r12 0021 #define rD3 r15 0022 #define rW0 r16 /* working registers */ 0023 #define rW1 r17 0024 #define rW2 r18 0025 #define rW3 r19 0026 #define rW4 r20 0027 #define rW5 r21 0028 #define rW6 r22 0029 #define rW7 r23 0030 #define rI0 r24 /* IV */ 0031 #define rI1 r25 0032 #define rI2 r26 0033 #define rI3 r27 0034 #define rG0 r28 /* endian reversed tweak (XTS mode) */ 0035 #define rG1 r29 0036 #define rG2 r30 0037 #define rG3 r31
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