powerpc/boot/ppc_asm.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef _PPC64_PPC_ASM_H
0003 #define _PPC64_PPC_ASM_H
0004 /*
0005  *
0006  * Definitions used by various bits of low-level assembly code on PowerPC.
0007  *
0008  * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
0009  */
0010
0011 /* Condition Register Bit Fields */
0012
0013 #define cr0 0
0014 #define cr1 1
0015 #define cr2 2
0016 #define cr3 3
0017 #define cr4 4
0018 #define cr5 5
0019 #define cr6 6
0020 #define cr7 7
0021
0022
0023 /* General Purpose Registers (GPRs) */
0024
0025 #define r0  0
0026 #define r1  1
0027 #define r2  2
0028 #define r3  3
0029 #define r4  4
0030 #define r5  5
0031 #define r6  6
0032 #define r7  7
0033 #define r8  8
0034 #define r9  9
0035 #define r10 10
0036 #define r11 11
0037 #define r12 12
0038 #define r13 13
0039 #define r14 14
0040 #define r15 15
0041 #define r16 16
0042 #define r17 17
0043 #define r18 18
0044 #define r19 19
0045 #define r20 20
0046 #define r21 21
0047 #define r22 22
0048 #define r23 23
0049 #define r24 24
0050 #define r25 25
0051 #define r26 26
0052 #define r27 27
0053 #define r28 28
0054 #define r29 29
0055 #define r30 30
0056 #define r31 31
0057
0058 #define SPRN_TBRL   268
0059 #define SPRN_TBRU   269
0060 #define SPRN_HSRR0  0x13A   /* Hypervisor Save/Restore 0 */
0061 #define SPRN_HSRR1  0x13B   /* Hypervisor Save/Restore 1 */
0062
0063 #define MSR_LE      0x0000000000000001
0064
0065 #define FIXUP_ENDIAN                           \
0066     tdi   0,0,0x48;   /* Reverse endian of b . + 8      */ \
0067     b     $+44;   /* Skip trampoline if endian is good  */ \
0068     .long 0xa600607d; /* mfmsr r11              */ \
0069     .long 0x01006b69; /* xori r11,r11,1         */ \
0070     .long 0x00004039; /* li r10,0               */ \
0071     .long 0x6401417d; /* mtmsrd r10,1           */ \
0072     .long 0x05009f42; /* bcl 20,31,$+4          */ \
0073     .long 0xa602487d; /* mflr r10               */ \
0074     .long 0x14004a39; /* addi r10,r10,20            */ \
0075     .long 0xa6035a7d; /* mtsrr0 r10             */ \
0076     .long 0xa6037b7d; /* mtsrr1 r11             */ \
0077     .long 0x2400004c  /* rfid               */
0078
0079 #ifdef CONFIG_PPC_8xx
0080 #define MFTBL(dest)         mftb dest
0081 #define MFTBU(dest)         mftbu dest
0082 #else
0083 #define MFTBL(dest)         mfspr dest, SPRN_TBRL
0084 #define MFTBU(dest)         mfspr dest, SPRN_TBRU
0085 #endif
0086
0087 #endif /* _PPC64_PPC_ASM_H */