powerpc/boot/mpc8xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MPC8xx support functions
0004  *
0005  * Author: Scott Wood <scottwood@freescale.com>
0006  *
0007  * Copyright (c) 2007 Freescale Semiconductor, Inc.
0008  */
0009
0010 #include "ops.h"
0011 #include "types.h"
0012 #include "fsl-soc.h"
0013 #include "mpc8xx.h"
0014 #include "stdio.h"
0015 #include "io.h"
0016
0017 #define MPC8XX_PLPRCR (0x284/4) /* PLL and Reset Control Register */
0018
0019 /* Return system clock from crystal frequency */
0020 u32 mpc885_get_clock(u32 crystal)
0021 {
0022     u32 *immr;
0023     u32 plprcr;
0024     int mfi, mfn, mfd, pdf;
0025     u32 ret;
0026
0027     immr = fsl_get_immr();
0028     if (!immr) {
0029         printf("mpc885_get_clock: Couldn't get IMMR base.\r\n");
0030         return 0;
0031     }
0032
0033     plprcr = in_be32(&immr[MPC8XX_PLPRCR]);
0034
0035     mfi = (plprcr >> 16) & 15;
0036     if (mfi < 5) {
0037         printf("Warning: PLPRCR[MFI] value of %d out-of-bounds\r\n",
0038                mfi);
0039         mfi = 5;
0040     }
0041
0042     pdf = (plprcr >> 1) & 0xf;
0043     mfd = (plprcr >> 22) & 0x1f;
0044     mfn = (plprcr >> 27) & 0x1f;
0045
0046     ret = crystal * mfi;
0047
0048     if (mfn != 0)
0049         ret += crystal * mfn / (mfd + 1);
0050
0051     return ret / (pdf + 1);
0052 }
0053
0054 /* Set common device tree fields based on the given clock frequencies. */
0055 void mpc8xx_set_clocks(u32 sysclk)
0056 {
0057     void *node;
0058
0059     dt_fixup_cpu_clocks(sysclk, sysclk / 16, sysclk);
0060
0061     node = finddevice("/soc/cpm");
0062     if (node)
0063         setprop(node, "clock-frequency", &sysclk, 4);
0064
0065     node = finddevice("/soc/cpm/brg");
0066     if (node)
0067         setprop(node, "clock-frequency", &sysclk, 4);
0068 }
0069
0070 int mpc885_fixup_clocks(u32 crystal)
0071 {
0072     u32 sysclk = mpc885_get_clock(crystal);
0073     if (!sysclk)
0074         return 0;
0075
0076     mpc8xx_set_clocks(sysclk);
0077     return 1;
0078 }