0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
0004 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
0005 *
0006 * XPedite5370 3U VPX single-board computer based on MPC8572E
0007 */
0008
0009 /dts-v1/;
0010 / {
0011 model = "xes,xpedite5370";
0012 compatible = "xes,xpedite5370", "xes,MPC8572";
0013 #address-cells = <2>;
0014 #size-cells = <2>;
0015
0016 aliases {
0017 ethernet0 = &enet0;
0018 ethernet1 = &enet1;
0019 serial0 = &serial0;
0020 serial1 = &serial1;
0021 pci1 = &pci1;
0022 pci2 = &pci2;
0023 };
0024
0025 cpus {
0026 #address-cells = <1>;
0027 #size-cells = <0>;
0028
0029 PowerPC,8572@0 {
0030 device_type = "cpu";
0031 reg = <0x0>;
0032 d-cache-line-size = <32>; // 32 bytes
0033 i-cache-line-size = <32>; // 32 bytes
0034 d-cache-size = <0x8000>; // L1, 32K
0035 i-cache-size = <0x8000>; // L1, 32K
0036 timebase-frequency = <0>;
0037 bus-frequency = <0>;
0038 clock-frequency = <0>;
0039 next-level-cache = <&L2>;
0040 };
0041
0042 PowerPC,8572@1 {
0043 device_type = "cpu";
0044 reg = <0x1>;
0045 d-cache-line-size = <32>; // 32 bytes
0046 i-cache-line-size = <32>; // 32 bytes
0047 d-cache-size = <0x8000>; // L1, 32K
0048 i-cache-size = <0x8000>; // L1, 32K
0049 timebase-frequency = <0>;
0050 bus-frequency = <0>;
0051 clock-frequency = <0>;
0052 next-level-cache = <&L2>;
0053 };
0054 };
0055
0056 memory {
0057 device_type = "memory";
0058 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
0059 };
0060
0061 localbus@ef005000 {
0062 #address-cells = <2>;
0063 #size-cells = <1>;
0064 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
0065 reg = <0 0xef005000 0 0x1000>;
0066 interrupts = <19 2>;
0067 interrupt-parent = <&mpic>;
0068 /* Local bus region mappings */
0069 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
0070 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
0071 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
0072 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
0073
0074 nor-boot@0,0 {
0075 compatible = "amd,s29gl01gp", "cfi-flash";
0076 bank-width = <2>;
0077 reg = <0 0 0x8000000>; /* 128MB */
0078 #address-cells = <1>;
0079 #size-cells = <1>;
0080 partition@0 {
0081 label = "Primary user space";
0082 reg = <0x00000000 0x6f00000>; /* 111 MB */
0083 };
0084 partition@6f00000 {
0085 label = "Primary kernel";
0086 reg = <0x6f00000 0x1000000>; /* 16 MB */
0087 };
0088 partition@7f00000 {
0089 label = "Primary DTB";
0090 reg = <0x7f00000 0x40000>; /* 256 KB */
0091 };
0092 partition@7f40000 {
0093 label = "Primary U-Boot environment";
0094 reg = <0x7f40000 0x40000>; /* 256 KB */
0095 };
0096 partition@7f80000 {
0097 label = "Primary U-Boot";
0098 reg = <0x7f80000 0x80000>; /* 512 KB */
0099 read-only;
0100 };
0101 };
0102
0103 nor-alternate@1,0 {
0104 compatible = "amd,s29gl01gp", "cfi-flash";
0105 bank-width = <2>;
0106 //reg = <0xf0000000 0x08000000>; /* 128MB */
0107 reg = <1 0 0x8000000>; /* 128MB */
0108 #address-cells = <1>;
0109 #size-cells = <1>;
0110 partition@0 {
0111 label = "Secondary user space";
0112 reg = <0x00000000 0x6f00000>; /* 111 MB */
0113 };
0114 partition@6f00000 {
0115 label = "Secondary kernel";
0116 reg = <0x6f00000 0x1000000>; /* 16 MB */
0117 };
0118 partition@7f00000 {
0119 label = "Secondary DTB";
0120 reg = <0x7f00000 0x40000>; /* 256 KB */
0121 };
0122 partition@7f40000 {
0123 label = "Secondary U-Boot environment";
0124 reg = <0x7f40000 0x40000>; /* 256 KB */
0125 };
0126 partition@7f80000 {
0127 label = "Secondary U-Boot";
0128 reg = <0x7f80000 0x80000>; /* 512 KB */
0129 read-only;
0130 };
0131 };
0132
0133 nand@2,0 {
0134 #address-cells = <1>;
0135 #size-cells = <1>;
0136 /*
0137 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
0138 * Micron MT29F8G08DAA (2x 512 MB), or Micron
0139 * MT29F16G08FAA (2x 1 GB), depending on the build
0140 * configuration
0141 */
0142 compatible = "fsl,mpc8572-fcm-nand",
0143 "fsl,elbc-fcm-nand";
0144 reg = <2 0 0x40000>;
0145 /* U-Boot should fix this up if chip size > 1 GB */
0146 partition@0 {
0147 label = "NAND Filesystem";
0148 reg = <0 0x40000000>;
0149 };
0150 };
0151
0152 };
0153
0154 soc8572@ef000000 {
0155 #address-cells = <1>;
0156 #size-cells = <1>;
0157 device_type = "soc";
0158 compatible = "fsl,mpc8572-immr", "simple-bus";
0159 ranges = <0x0 0 0xef000000 0x100000>;
0160 bus-frequency = <0>; // Filled out by uboot.
0161
0162 ecm-law@0 {
0163 compatible = "fsl,ecm-law";
0164 reg = <0x0 0x1000>;
0165 fsl,num-laws = <12>;
0166 };
0167
0168 ecm@1000 {
0169 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
0170 reg = <0x1000 0x1000>;
0171 interrupts = <17 2>;
0172 interrupt-parent = <&mpic>;
0173 };
0174
0175 memory-controller@2000 {
0176 compatible = "fsl,mpc8572-memory-controller";
0177 reg = <0x2000 0x1000>;
0178 interrupt-parent = <&mpic>;
0179 interrupts = <18 2>;
0180 };
0181
0182 memory-controller@6000 {
0183 compatible = "fsl,mpc8572-memory-controller";
0184 reg = <0x6000 0x1000>;
0185 interrupt-parent = <&mpic>;
0186 interrupts = <18 2>;
0187 };
0188
0189 L2: l2-cache-controller@20000 {
0190 compatible = "fsl,mpc8572-l2-cache-controller";
0191 reg = <0x20000 0x1000>;
0192 cache-line-size = <32>; // 32 bytes
0193 cache-size = <0x100000>; // L2, 1M
0194 interrupt-parent = <&mpic>;
0195 interrupts = <16 2>;
0196 };
0197
0198 i2c@3000 {
0199 #address-cells = <1>;
0200 #size-cells = <0>;
0201 cell-index = <0>;
0202 compatible = "fsl-i2c";
0203 reg = <0x3000 0x100>;
0204 interrupts = <43 2>;
0205 interrupt-parent = <&mpic>;
0206 dfsrr;
0207
0208 temp-sensor@48 {
0209 compatible = "dallas,ds1631", "dallas,ds1621";
0210 reg = <0x48>;
0211 };
0212
0213 temp-sensor@4c {
0214 compatible = "adi,adt7461";
0215 reg = <0x4c>;
0216 };
0217
0218 cpu-supervisor@51 {
0219 compatible = "dallas,ds4510";
0220 reg = <0x51>;
0221 };
0222
0223 eeprom@54 {
0224 compatible = "atmel,at24c128b";
0225 reg = <0x54>;
0226 };
0227
0228 rtc@68 {
0229 compatible = "st,m41t00",
0230 "dallas,ds1338";
0231 reg = <0x68>;
0232 };
0233
0234 pcie-switch@70 {
0235 compatible = "plx,pex8518";
0236 reg = <0x70>;
0237 };
0238
0239 gpio1: gpio@18 {
0240 compatible = "nxp,pca9557";
0241 reg = <0x18>;
0242 #gpio-cells = <2>;
0243 gpio-controller;
0244 polarity = <0x00>;
0245 };
0246
0247 gpio2: gpio@1c {
0248 compatible = "nxp,pca9557";
0249 reg = <0x1c>;
0250 #gpio-cells = <2>;
0251 gpio-controller;
0252 polarity = <0x00>;
0253 };
0254
0255 gpio3: gpio@1e {
0256 compatible = "nxp,pca9557";
0257 reg = <0x1e>;
0258 #gpio-cells = <2>;
0259 gpio-controller;
0260 polarity = <0x00>;
0261 };
0262
0263 gpio4: gpio@1f {
0264 compatible = "nxp,pca9557";
0265 reg = <0x1f>;
0266 #gpio-cells = <2>;
0267 gpio-controller;
0268 polarity = <0x00>;
0269 };
0270 };
0271
0272 i2c@3100 {
0273 #address-cells = <1>;
0274 #size-cells = <0>;
0275 cell-index = <1>;
0276 compatible = "fsl-i2c";
0277 reg = <0x3100 0x100>;
0278 interrupts = <43 2>;
0279 interrupt-parent = <&mpic>;
0280 dfsrr;
0281 };
0282
0283 dma@c300 {
0284 #address-cells = <1>;
0285 #size-cells = <1>;
0286 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0287 reg = <0xc300 0x4>;
0288 ranges = <0x0 0xc100 0x200>;
0289 cell-index = <1>;
0290 dma-channel@0 {
0291 compatible = "fsl,mpc8572-dma-channel",
0292 "fsl,eloplus-dma-channel";
0293 reg = <0x0 0x80>;
0294 cell-index = <0>;
0295 interrupt-parent = <&mpic>;
0296 interrupts = <76 2>;
0297 };
0298 dma-channel@80 {
0299 compatible = "fsl,mpc8572-dma-channel",
0300 "fsl,eloplus-dma-channel";
0301 reg = <0x80 0x80>;
0302 cell-index = <1>;
0303 interrupt-parent = <&mpic>;
0304 interrupts = <77 2>;
0305 };
0306 dma-channel@100 {
0307 compatible = "fsl,mpc8572-dma-channel",
0308 "fsl,eloplus-dma-channel";
0309 reg = <0x100 0x80>;
0310 cell-index = <2>;
0311 interrupt-parent = <&mpic>;
0312 interrupts = <78 2>;
0313 };
0314 dma-channel@180 {
0315 compatible = "fsl,mpc8572-dma-channel",
0316 "fsl,eloplus-dma-channel";
0317 reg = <0x180 0x80>;
0318 cell-index = <3>;
0319 interrupt-parent = <&mpic>;
0320 interrupts = <79 2>;
0321 };
0322 };
0323
0324 dma@21300 {
0325 #address-cells = <1>;
0326 #size-cells = <1>;
0327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
0328 reg = <0x21300 0x4>;
0329 ranges = <0x0 0x21100 0x200>;
0330 cell-index = <0>;
0331 dma-channel@0 {
0332 compatible = "fsl,mpc8572-dma-channel",
0333 "fsl,eloplus-dma-channel";
0334 reg = <0x0 0x80>;
0335 cell-index = <0>;
0336 interrupt-parent = <&mpic>;
0337 interrupts = <20 2>;
0338 };
0339 dma-channel@80 {
0340 compatible = "fsl,mpc8572-dma-channel",
0341 "fsl,eloplus-dma-channel";
0342 reg = <0x80 0x80>;
0343 cell-index = <1>;
0344 interrupt-parent = <&mpic>;
0345 interrupts = <21 2>;
0346 };
0347 dma-channel@100 {
0348 compatible = "fsl,mpc8572-dma-channel",
0349 "fsl,eloplus-dma-channel";
0350 reg = <0x100 0x80>;
0351 cell-index = <2>;
0352 interrupt-parent = <&mpic>;
0353 interrupts = <22 2>;
0354 };
0355 dma-channel@180 {
0356 compatible = "fsl,mpc8572-dma-channel",
0357 "fsl,eloplus-dma-channel";
0358 reg = <0x180 0x80>;
0359 cell-index = <3>;
0360 interrupt-parent = <&mpic>;
0361 interrupts = <23 2>;
0362 };
0363 };
0364
0365 /* eTSEC 1 */
0366 enet0: ethernet@24000 {
0367 #address-cells = <1>;
0368 #size-cells = <1>;
0369 cell-index = <0>;
0370 device_type = "network";
0371 model = "eTSEC";
0372 compatible = "gianfar";
0373 reg = <0x24000 0x1000>;
0374 ranges = <0x0 0x24000 0x1000>;
0375 local-mac-address = [ 00 00 00 00 00 00 ];
0376 interrupts = <29 2 30 2 34 2>;
0377 interrupt-parent = <&mpic>;
0378 tbi-handle = <&tbi0>;
0379 phy-handle = <&phy0>;
0380 phy-connection-type = "sgmii";
0381
0382 mdio@520 {
0383 #address-cells = <1>;
0384 #size-cells = <0>;
0385 compatible = "fsl,gianfar-mdio";
0386 reg = <0x520 0x20>;
0387
0388 phy0: ethernet-phy@1 {
0389 interrupt-parent = <&mpic>;
0390 interrupts = <8 1>;
0391 reg = <0x1>;
0392 };
0393 phy1: ethernet-phy@2 {
0394 interrupt-parent = <&mpic>;
0395 interrupts = <8 1>;
0396 reg = <0x2>;
0397 };
0398 tbi0: tbi-phy@11 {
0399 reg = <0x11>;
0400 device_type = "tbi-phy";
0401 };
0402 };
0403 };
0404
0405 /* eTSEC 2 */
0406 enet1: ethernet@25000 {
0407 #address-cells = <1>;
0408 #size-cells = <1>;
0409 cell-index = <1>;
0410 device_type = "network";
0411 model = "eTSEC";
0412 compatible = "gianfar";
0413 reg = <0x25000 0x1000>;
0414 ranges = <0x0 0x25000 0x1000>;
0415 local-mac-address = [ 00 00 00 00 00 00 ];
0416 interrupts = <35 2 36 2 40 2>;
0417 interrupt-parent = <&mpic>;
0418 tbi-handle = <&tbi1>;
0419 phy-handle = <&phy1>;
0420 phy-connection-type = "sgmii";
0421
0422 mdio@520 {
0423 #address-cells = <1>;
0424 #size-cells = <0>;
0425 compatible = "fsl,gianfar-tbi";
0426 reg = <0x520 0x20>;
0427
0428 tbi1: tbi-phy@11 {
0429 reg = <0x11>;
0430 device_type = "tbi-phy";
0431 };
0432 };
0433 };
0434
0435 /* UART0 */
0436 serial0: serial@4500 {
0437 cell-index = <0>;
0438 device_type = "serial";
0439 compatible = "fsl,ns16550", "ns16550";
0440 reg = <0x4500 0x100>;
0441 clock-frequency = <0>;
0442 interrupts = <42 2>;
0443 interrupt-parent = <&mpic>;
0444 };
0445
0446 /* UART1 */
0447 serial1: serial@4600 {
0448 cell-index = <1>;
0449 device_type = "serial";
0450 compatible = "fsl,ns16550", "ns16550";
0451 reg = <0x4600 0x100>;
0452 clock-frequency = <0>;
0453 interrupts = <42 2>;
0454 interrupt-parent = <&mpic>;
0455 };
0456
0457 global-utilities@e0000 { //global utilities block
0458 compatible = "fsl,mpc8572-guts";
0459 reg = <0xe0000 0x1000>;
0460 fsl,has-rstcr;
0461 };
0462
0463 msi@41600 {
0464 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
0465 reg = <0x41600 0x80>;
0466 msi-available-ranges = <0 0x100>;
0467 interrupts = <
0468 0xe0 0
0469 0xe1 0
0470 0xe2 0
0471 0xe3 0
0472 0xe4 0
0473 0xe5 0
0474 0xe6 0
0475 0xe7 0>;
0476 interrupt-parent = <&mpic>;
0477 };
0478
0479 crypto@30000 {
0480 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
0481 "fsl,sec2.1", "fsl,sec2.0";
0482 reg = <0x30000 0x10000>;
0483 interrupts = <45 2 58 2>;
0484 interrupt-parent = <&mpic>;
0485 fsl,num-channels = <4>;
0486 fsl,channel-fifo-len = <24>;
0487 fsl,exec-units-mask = <0x9fe>;
0488 fsl,descriptor-types-mask = <0x3ab0ebf>;
0489 };
0490
0491 mpic: pic@40000 {
0492 interrupt-controller;
0493 #address-cells = <0>;
0494 #interrupt-cells = <2>;
0495 reg = <0x40000 0x40000>;
0496 compatible = "chrp,open-pic";
0497 device_type = "open-pic";
0498 };
0499
0500 gpio0: gpio@f000 {
0501 compatible = "fsl,mpc8572-gpio";
0502 reg = <0xf000 0x1000>;
0503 interrupts = <47 2>;
0504 interrupt-parent = <&mpic>;
0505 #gpio-cells = <2>;
0506 gpio-controller;
0507 };
0508
0509 gpio-leds {
0510 compatible = "gpio-leds";
0511
0512 heartbeat {
0513 label = "Heartbeat";
0514 gpios = <&gpio0 4 1>;
0515 linux,default-trigger = "heartbeat";
0516 };
0517
0518 yellow {
0519 label = "Yellow";
0520 gpios = <&gpio0 5 1>;
0521 };
0522
0523 red {
0524 label = "Red";
0525 gpios = <&gpio0 6 1>;
0526 };
0527
0528 green {
0529 label = "Green";
0530 gpios = <&gpio0 7 1>;
0531 };
0532 };
0533
0534 /* PME (pattern-matcher) */
0535 pme@10000 {
0536 compatible = "fsl,mpc8572-pme", "pme8572";
0537 reg = <0x10000 0x5000>;
0538 interrupts = <57 2 64 2 65 2 66 2 67 2>;
0539 interrupt-parent = <&mpic>;
0540 };
0541
0542 tlu@2f000 {
0543 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0544 reg = <0x2f000 0x1000>;
0545 interrupts = <61 2>;
0546 interrupt-parent = <&mpic>;
0547 };
0548
0549 tlu@15000 {
0550 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
0551 reg = <0x15000 0x1000>;
0552 interrupts = <75 2>;
0553 interrupt-parent = <&mpic>;
0554 };
0555 };
0556
0557 /*
0558 * PCI Express controller 3 @ ef008000 is not used.
0559 * This would have been pci0 on other mpc85xx platforms.
0560 */
0561
0562 /* PCI Express controller 2, wired to VPX P1,P2 backplane */
0563 pci1: pcie@ef009000 {
0564 compatible = "fsl,mpc8548-pcie";
0565 device_type = "pci";
0566 #interrupt-cells = <1>;
0567 #size-cells = <2>;
0568 #address-cells = <3>;
0569 reg = <0 0xef009000 0 0x1000>;
0570 bus-range = <0 255>;
0571 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
0572 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
0573 clock-frequency = <33333333>;
0574 interrupt-parent = <&mpic>;
0575 interrupts = <25 2>;
0576 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0577 interrupt-map = <
0578 /* IDSEL 0x0 */
0579 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
0580 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
0581 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
0582 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
0583 >;
0584 pcie@0 {
0585 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
0586 #size-cells = <2>;
0587 #address-cells = <3>;
0588 device_type = "pci";
0589 ranges = <0x2000000 0x0 0xc0000000
0590 0x2000000 0x0 0xc0000000
0591 0x0 0x10000000
0592
0593 0x1000000 0x0 0x0
0594 0x1000000 0x0 0x0
0595 0x0 0x100000>;
0596 };
0597 };
0598
0599 /* PCI Express controller 1, wired to PEX8518 PCIe switch */
0600 pci2: pcie@ef00a000 {
0601 compatible = "fsl,mpc8548-pcie";
0602 device_type = "pci";
0603 #interrupt-cells = <1>;
0604 #size-cells = <2>;
0605 #address-cells = <3>;
0606 reg = <0 0xef00a000 0 0x1000>;
0607 bus-range = <0 255>;
0608 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
0609 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
0610 clock-frequency = <33333333>;
0611 interrupt-parent = <&mpic>;
0612 interrupts = <26 2>;
0613 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0614 interrupt-map = <
0615 /* IDSEL 0x0 */
0616 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
0617 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
0618 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
0619 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
0620 >;
0621 pcie@0 {
0622 reg = <0x0 0x0 0x0 0x0 0x0>;
0623 #size-cells = <2>;
0624 #address-cells = <3>;
0625 device_type = "pci";
0626 ranges = <0x2000000 0x0 0x80000000
0627 0x2000000 0x0 0x80000000
0628 0x0 0x40000000
0629
0630 0x1000000 0x0 0x0
0631 0x1000000 0x0 0x0
0632 0x0 0x100000>;
0633 };
0634 };
0635 };
